;; sllv, slt, slti, sltiu, sltu, sra, srav, srl, srlv, sub, subu, wsbh,
;; xor, xori
(define_insn_reservation "r74k_int_arith" 2
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "arith,const,shift,slt,clz"))
"r74k_alu")
(define_insn_reservation "r74k_int_nop" 0
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "nop"))
"nothing")
(define_insn_reservation "r74k_int_cmove" 4
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "condmove"))
"r74k_agen*2")
;; MDU: fully pipelined multiplier
;; mult, madd, msub - delivers result to hi/lo in 4 cycle (pipelined)
(define_insn_reservation "r74k_int_mult" 4
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "imul,imadd"))
"r74k_alu+r74k_mul")
;; mul - delivers result to general register in 7 cycles
(define_insn_reservation "r74k_int_mul3" 7
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "imul3"))
"r74k_alu+r74k_mul")
;; mfhi, mflo, mflhxu - deliver result to gpr in 7 cycles
(define_insn_reservation "r74k_int_mfhilo" 7
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "mfhilo"))
"r74k_alu+r74k_mul")
;; mthi, mtlo, mtlhx - deliver result to hi/lo, thence madd, handled as bypass
(define_insn_reservation "r74k_int_mthilo" 7
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "mthilo"))
"r74k_alu+r74k_mul")
;; div - default to 50 cycles for 32bit operands. Faster for 8 bit,
;; but is tricky to identify.
(define_insn_reservation "r74k_int_div" 50
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "idiv"))
"r74k_alu+r74k_mul*50")
;; call
(define_insn_reservation "r74k_int_call" 1
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "call"))
"r74k_agen")
;; branch/jump
(define_insn_reservation "r74k_int_jump" 1
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "branch,jump"))
"r74k_agen")
;; loads: lb, lbu, lh, lhu, ll, lw, lwl, lwr, lwpc, lwxs
;; prefetch: prefetch, prefetchx
(define_insn_reservation "r74k_int_load" 3
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "load,prefetch,prefetchx"))
"r74k_agen")
;; stores
(define_insn_reservation "r74k_int_store" 1
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(and (eq_attr "type" "store")
(eq_attr "mode" "!unknown")))
"r74k_agen")
;; affects scheduling via log links, but not used here).
;;
(define_insn_reservation "r74k_unknown" 1
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "unknown"))
"r74k_alu")
(define_insn_reservation "r74k_multi" 10
- (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1")
+ (and (eq_attr "cpu" "74kc,74kf2_1,74kf1_1,74kf3_2")
(eq_attr "type" "multi"))
"(r74k_alu+r74k_agen)*10")
(eq_attr "type" "fadd,fabs,fneg"))
"r74k_fpu_arith*2")
+(define_insn_reservation "r74kf3_2_fadd" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "fadd,fabs,fneg"))
+ "r74k_fpu_arith")
+
;; fmove, fcmove
(define_insn_reservation "r74kf1_1_fmove" 4
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fmove"))
"r74k_fpu_arith*2")
+(define_insn_reservation "r74kf3_2_fmove" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "fmove"))
+ "r74k_fpu_arith")
+
;; fload
(define_insn_reservation "r74kf1_1_fload" 4
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fpload,fpidxload"))
"r74k_agen+(r74k_fpu_ldst*2)")
+(define_insn_reservation "r74kf3_2_fload" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "fpload,fpidxload"))
+ "r74k_agen+r74k_fpu_ldst")
+
;; fstore
(define_insn_reservation "r74kf1_1_fstore" 1
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fpstore,fpidxstore"))
"r74k_agen+(r74k_fpu_ldst*2)")
+(define_insn_reservation "r74kf3_2_fstore" 1
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "fpstore,fpidxstore"))
+ "r74k_agen+r74k_fpu_ldst")
+
;; fmul, fmadd
(define_insn_reservation "r74kf1_1_fmul_sf" 4
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*2")
+(define_insn_reservation "r74kf3_2_fmul_sf" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "SF")))
+ "r74k_fpu_arith")
+
(define_insn_reservation "r74kf1_1_fmul_df" 5
(and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "fmul,fmadd")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*4")
+(define_insn_reservation "r74kf3_2_fmul_df" 7
+ (and (eq_attr "cpu" "74kf3_2")
+ (and (eq_attr "type" "fmul,fmadd")
+ (eq_attr "mode" "DF")))
+ "r74k_fpu_arith*2")
+
;; fdiv, fsqrt
(define_insn_reservation "r74kf1_1_fdiv_sf" 17
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*28")
+(define_insn_reservation "r74kf3_2_fdiv_sf" 25
+ (and (eq_attr "cpu" "74kf3_2")
+ (and (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "SF")))
+ "r74k_fpu_arith*14")
+
(define_insn_reservation "r74kf1_1_fdiv_df" 32
(and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "fdiv,fsqrt")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*58")
+(define_insn_reservation "r74kf3_2_fdiv_df" 48
+ (and (eq_attr "cpu" "74kf3_2")
+ (and (eq_attr "type" "fdiv,fsqrt")
+ (eq_attr "mode" "DF")))
+ "r74k_fpu_arith*29")
+
;; frsqrt
(define_insn_reservation "r74kf1_1_frsqrt_sf" 17
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "mode" "SF")))
"r74k_fpu_arith*28")
+(define_insn_reservation "r74kf3_2_frsqrt_sf" 25
+ (and (eq_attr "cpu" "74kf3_2")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "SF")))
+ "r74k_fpu_arith*14")
+
(define_insn_reservation "r74kf1_1_frsqrt_df" 36
(and (eq_attr "cpu" "74kf1_1")
(and (eq_attr "type" "frsqrt")
(eq_attr "mode" "DF")))
"r74k_fpu_arith*62")
+(define_insn_reservation "r74kf3_2_frsqrt_df" 54
+ (and (eq_attr "cpu" "74kf3_2")
+ (and (eq_attr "type" "frsqrt")
+ (eq_attr "mode" "DF")))
+ "r74k_fpu_arith*31")
+
;; fcmp
(define_insn_reservation "r74kf1_1_fcmp" 4
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fcmp"))
"r74k_fpu_arith*2")
+(define_insn_reservation "r74kf3_2_fcmp" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "fcmp"))
+ "r74k_fpu_arith")
+
;; fcvt
(define_insn_reservation "r74kf1_1_fcvt" 4
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "fcvt"))
"r74k_fpu_arith*2")
+(define_insn_reservation "r74kf3_2_fcvt" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "fcvt"))
+ "r74k_fpu_arith")
+
;; fxfer (MTC1, DMTC1: latency is 4) (MFC1, DMFC1: latency is 1)
(define_insn_reservation "r74kf1_1_fxfer_to_c1" 4
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "mtc"))
"r74k_fpu_arith*2")
+(define_insn_reservation "r74kf3_2_fxfer_to_c1" 6
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "mtc"))
+ "r74k_fpu_arith")
+
(define_insn_reservation "r74kf1_1_fxfer_from_c1" 1
(and (eq_attr "cpu" "74kf1_1")
(eq_attr "type" "mfc"))
(and (eq_attr "cpu" "74kf2_1")
(eq_attr "type" "mfc"))
"r74k_fpu_arith*2")
+
+(define_insn_reservation "r74kf3_2_fxfer_from_c1" 1
+ (and (eq_attr "cpu" "74kf3_2")
+ (eq_attr "type" "mfc"))
+ "r74k_fpu_arith")