ARM: dts: ls1021a: update pcie nodes for dt-schema check

Break up long values to pass dt-schema checks.

Signed-off-by: Li Yang <leoyang.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2f9ea0b..fa4adfd 100644 (file)
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -839,8 +839,8 @@
 
                pcie@3400000 {
                        compatible = "fsl,ls1021a-pcie";
-                       reg = <0x00 0x03400000 0x0 0x00010000   /* controller registers */
-                              0x40 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg = <0x00 0x03400000 0x0 0x00010000>, /* controller registers */
+                             <0x40 0x00000000 0x0 0x00002000>; /* configuration space */
                        reg-names = "regs", "config";
                        interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
                        fsl,pcie-scfg = <&scfg 0>;
@@ -849,8 +849,8 @@
                        device_type = "pci";
                        num-viewport = <6>;
                        bus-range = <0x0 0xff>;
-                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000   /* downstream I/O */
-                                 0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                       ranges = <0x81000000 0x0 0x00000000 0x40 0x00010000 0x0 0x00010000>, /* downstream I/O */
+                                <0x82000000 0x0 0x40000000 0x40 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                        msi-parent = <&msi1>, <&msi2>;
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;
@@ -863,8 +863,8 @@
 
                pcie@3500000 {
                        compatible = "fsl,ls1021a-pcie";
-                       reg = <0x00 0x03500000 0x0 0x00010000   /* controller registers */
-                              0x48 0x00000000 0x0 0x00002000>; /* configuration space */
+                       reg = <0x00 0x03500000 0x0 0x00010000>, /* controller registers */
+                             <0x48 0x00000000 0x0 0x00002000>; /* configuration space */
                        reg-names = "regs", "config";
                        interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>;
                        fsl,pcie-scfg = <&scfg 1>;
@@ -873,8 +873,8 @@
                        device_type = "pci";
                        num-viewport = <6>;
                        bus-range = <0x0 0xff>;
-                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000   /* downstream I/O */
-                                 0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
+                       ranges = <0x81000000 0x0 0x00000000 0x48 0x00010000 0x0 0x00010000>, /* downstream I/O */
+                                <0x82000000 0x0 0x40000000 0x48 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */
                        msi-parent = <&msi1>, <&msi2>;
                        #interrupt-cells = <1>;
                        interrupt-map-mask = <0 0 0 7>;