arm64: dts: exynos: TM2 - add support for MFC video codec device
authorMarek Szyprowski <m.szyprowski@samsung.com>
Fri, 18 Nov 2016 12:23:13 +0000 (13:23 +0100)
committerKrzysztof Kozlowski <krzk@kernel.org>
Fri, 18 Nov 2016 12:26:53 +0000 (14:26 +0200)
This patch adds device nodes for MFC video codec device to Exynos5433 SoC
dtsi and proper initial clock configuration to TM2 dts.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
arch/arm64/boot/dts/exynos/exynos5433-tm2.dts
arch/arm64/boot/dts/exynos/exynos5433.dtsi

index 6f506dd..ce41781 100644 (file)
                                 <&cmu_top CLK_ACLK_GSCL_333>;
 };
 
+&cmu_mfc {
+       assigned-clocks = <&cmu_mfc CLK_MOUT_ACLK_MFC_400_USER>;
+       assigned-clock-parents = <&cmu_top CLK_ACLK_MFC_400>;
+};
+
 &cmu_mscl {
        assigned-clocks = <&cmu_mscl CLK_MOUT_ACLK_MSCL_400_USER>,
                          <&cmu_mscl CLK_MOUT_SCLK_JPEG_USER>,
index 1d47480..64226d5 100644 (file)
                        iommus = <&sysmmu_jpeg>;
                };
 
+               mfc: codec@152E0000 {
+                       compatible = "samsung,exynos5433-mfc";
+                       reg = <0x152E0000 0x10000>;
+                       interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk", "aclk_xiu";
+                       clocks = <&cmu_mfc CLK_PCLK_MFC>,
+                                <&cmu_mfc CLK_ACLK_MFC>,
+                                <&cmu_mfc CLK_ACLK_XIU_MFCX>;
+                       iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
+                       iommu-names = "left", "right";
+               };
+
                sysmmu_decon0x: sysmmu@0x13a00000 {
                        compatible = "samsung,exynos-sysmmu";
                        reg = <0x13a00000 0x1000>;
                        #iommu-cells = <0>;
                };
 
+               sysmmu_mfc_0: sysmmu@0x15200000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x15200000 0x1000>;
+                       interrupts = <GIC_SPI 352 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
+                                <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
+                       #iommu-cells = <0>;
+               };
+
+               sysmmu_mfc_1: sysmmu@0x15210000 {
+                       compatible = "samsung,exynos-sysmmu";
+                       reg = <0x15210000 0x1000>;
+                       interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>;
+                       clock-names = "pclk", "aclk";
+                       clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
+                                <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
+                       #iommu-cells = <0>;
+               };
+
                serial_0: serial@14c10000 {
                        compatible = "samsung,exynos5433-uart";
                        reg = <0x14c10000 0x100>;