// Determine whether the vector instructions requirements represented by
// InstrInfo are compatible with the previous vsetvli instruction represented
// by this.
- bool isCompatible(const VSETVLIInfo &InstrInfo) const {
+ bool isCompatible(const VSETVLIInfo &InstrInfo, bool Strict) const {
assert(isValid() && InstrInfo.isValid() &&
"Can't compare invalid VSETVLIInfos");
assert(!InstrInfo.SEWLMULRatioOnly &&
// If the instruction doesn't need an AVLReg and the SEW matches, consider
// it compatible.
- if (InstrInfo.hasAVLReg() && InstrInfo.AVLReg == RISCV::NoRegister) {
+ if (!Strict && InstrInfo.hasAVLReg() &&
+ InstrInfo.AVLReg == RISCV::NoRegister) {
if (SEW == InstrInfo.SEW)
return true;
}
if (hasSameVTYPE(InstrInfo))
return true;
+ // Strict matches must ensure a full VTYPE match.
+ if (Strict)
+ return false;
+
// If this is a mask reg operation, it only cares about VLMAX.
// FIXME: Mask reg operations are probably ok if "this" VLMAX is larger
// than "InstrInfo".
// If the change is compatible with the input, we won't create a VSETVLI
// and should keep the predecessor.
- if (isCompatible(Other))
+ if (isCompatible(Other, /*Strict*/ true))
return *this;
// Otherwise just use whatever is in this block.
bool RISCVInsertVSETVLI::needVSETVLI(const VSETVLIInfo &Require,
const VSETVLIInfo &CurInfo) {
- if (CurInfo.isCompatible(Require))
+ if (CurInfo.isCompatible(Require, /*Strict*/ false))
return false;
// We didn't find a compatible value. If our AVL is a virtual register,
...
---
-# FIXME: We incorrectly merge info for %bb.1 into that for %bb.0, leading us to
-# skip a vsetvli for the PseudoVADD_VX_MF2 in %bb.3. In fact, the
-# PseudoVPOPC_M_B1 is given a vsetvli (e8,mf8) which, if control flow flows
-# through %bb.1 to %bb.3, misconfigures the PseudoVADD_VX_MF2.
name: vsetvli_vpopc
tracksRegLiveness: true
registers:
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.3:
; CHECK-NEXT: [[PHI:%[0-9]+]]:gpr = PHI [[DEF]], %bb.1, [[LWU]], %bb.2
+ ; CHECK-NEXT: dead $x0 = PseudoVSETVLIX0 killed $x0, 87, implicit-def $vl, implicit-def $vtype, implicit $vl
; CHECK-NEXT: [[PseudoVADD_VX_MF2_:%[0-9]+]]:vr = nsw PseudoVADD_VX_MF2 [[PseudoVLE32_V_MF2_MASK]], [[PHI]], -1, 5, implicit $vl, implicit $vtype
; CHECK-NEXT: $v0 = COPY [[PseudoVADD_VX_MF2_]]
; CHECK-NEXT: PseudoRET implicit $v0