dt-bindings: phy: add UniPhier PCIe PHY description

Add DT bindings for PHY interface built into PCIe controller implemented
in UniPhier SoCs.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>

diff --git a/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
new file mode 100644 (file)
index 0000000..1889d3b
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+++ b/Documentation/devicetree/bindings/phy/uniphier-pcie-phy.txt
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+Socionext UniPhier PCIe PHY bindings
+
+This describes the devicetree bindings for PHY interface built into
+PCIe controller implemented on Socionext UniPhier SoCs.
+
+Required properties:
+- compatible: Should contain one of the following:
+    "socionext,uniphier-ld20-pcie-phy" - for LD20 PHY
+    "socionext,uniphier-pxs3-pcie-phy" - for PXs3 PHY
+- reg: Specifies offset and length of the register set for the device.
+- #phy-cells: Must be zero.
+- clocks: A phandle to the clock gate for PCIe glue layer including
+       this phy.
+- resets: A phandle to the reset line for PCIe glue layer including
+       this phy.
+
+Optional properties:
+- socionext,syscon: A phandle to system control to set configurations
+       for phy.
+
+Refer to phy/phy-bindings.txt for the generic PHY binding properties.
+
+Example:
+       pcie_phy: phy@66038000 {
+               compatible = "socionext,uniphier-ld20-pcie-phy";
+               reg = <0x66038000 0x4000>;
+               #phy-cells = <0>;
+               clocks = <&sys_clk 24>;
+               resets = <&sys_rst 24>;
+               socionext,syscon = <&soc_glue>;
+       };