arm64: dts: ipq6018: Add the QPIC peripheral nodes

Add the QPIC BAM and QPIC NAND controller support and
enable the same in board DTS file.

Co-developed-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org>
Signed-off-by: Anusha Canchi Ramachandra Rao <anusharao@codeaurora.org>
Signed-off-by: Kathiravan T <kathirav@codeaurora.org>
Link: https://lore.kernel.org/r/1606734105-12414-2-git-send-email-kathirav@codeaurora.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>

diff --git a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
index e8eaa958c1992b4b9d602680d739f4e4d0a7017a..99cefe88f6f2369d4f0e25572ac23aa1dfdc5746 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
+++ b/arch/arm64/boot/dts/qcom/ipq6018-cp01-c1.dts
@@ -62,3 +62,19 @@
                bias-pull-down;
        };
 };
+
+&qpic_bam {
+       status = "okay";
+};
+
+&qpic_nand {
+       status = "okay";
+
+       nand@0 {
+               reg = <0>;
+
+               nand-ecc-strength = <4>;
+               nand-ecc-step-size = <512>;
+               nand-bus-width = <8>;
+       };
+};

diff --git a/arch/arm64/boot/dts/qcom/ipq6018.dtsi b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
index a94dac76bf3fbddd8c2f808f09b8bdc2d7c368e6..a366a05128c267e2a7c0dae8f13f9b6f1e083776 100644 (file)
--- a/arch/arm64/boot/dts/qcom/ipq6018.dtsi
+++ b/arch/arm64/boot/dts/qcom/ipq6018.dtsi
@@ -231,6 +231,17 @@
                                drive-strength = <8>;
                                bias-pull-down;
                        };
+
+                       qpic_pins: qpic-pins {
+                               pins = "gpio1", "gpio3", "gpio4",
+                                       "gpio5", "gpio6", "gpio7",
+                                       "gpio8", "gpio10", "gpio11",
+                                       "gpio12", "gpio13", "gpio14",
+                                       "gpio15", "gpio17";
+                               function = "qpic_pad";
+                               drive-strength = <8>;
+                               bias-disable;
+                       };
                };
 
                gcc: gcc@1800000 {
@@ -332,6 +343,36 @@
                        status = "disabled";
                };
 
+               qpic_bam: dma-controller@7984000 {
+                       compatible = "qcom,bam-v1.7.0";
+                       reg = <0x0 0x07984000 0x0 0x1a000>;
+                       interrupts = <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>;
+                       clocks = <&gcc GCC_QPIC_CLK>,
+                                <&gcc GCC_QPIC_AHB_CLK>;
+                       clock-names = "iface_clk", "bam_clk";
+                       #dma-cells = <1>;
+                       qcom,ee = <0>;
+                       status = "disabled";
+               };
+
+               qpic_nand: nand@79b0000 {
+                       compatible = "qcom,ipq6018-nand";
+                       reg = <0x0 0x079b0000 0x0 0x10000>;
+                       #address-cells = <1>;
+                       #size-cells = <0>;
+                       clocks = <&gcc GCC_QPIC_CLK>,
+                                <&gcc GCC_QPIC_AHB_CLK>;
+                       clock-names = "core", "aon";
+
+                       dmas = <&qpic_bam 0>,
+                               <&qpic_bam 1>,
+                               <&qpic_bam 2>;
+                       dma-names = "tx", "rx", "cmd";
+                       pinctrl-0 = <&qpic_pins>;
+                       pinctrl-names = "default";
+                       status = "disabled";
+               };
+
                intc: interrupt-controller@b000000 {
                        compatible = "qcom,msm-qgic2";
                        interrupt-controller;