GlobalISel: Verify G_BITCAST changes the type

Updated the AArch64 tests the best I could with my vague, inferred
understanding of AArch64 register banks. As far as I can tell, there
is only one 32-bit/64-bit type which will use the gpr register bank,
so we have to use the fpr bank for the other operand.

diff --git a/llvm/lib/CodeGen/MachineVerifier.cpp b/llvm/lib/CodeGen/MachineVerifier.cpp
index cfc6e38..c1a2c4e 100644 (file)
--- a/llvm/lib/CodeGen/MachineVerifier.cpp
+++ b/llvm/lib/CodeGen/MachineVerifier.cpp
@@ -1018,6 +1018,10 @@ void MachineVerifier::verifyPreISelGenericInstruction(const MachineInstr *MI) {
 
     if (SrcTy.getSizeInBits() != DstTy.getSizeInBits())
       report("bitcast sizes must match", MI);
+
+    if (SrcTy == DstTy)
+      report("bitcast must change the type", MI);
+
     break;
   }
   case TargetOpcode::G_INTTOPTR:

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
index 463d6c1..37d00df 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/arm64-regbankselect.mir
@@ -398,20 +398,23 @@ legalized:       true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: gpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: gpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 1, class: fpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 1, class: gpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0:gpr(s32) = COPY $w0
-# CHECK:    %1:gpr(s32) = G_BITCAST %0
+# FAST-NEXT:   %1:fpr(<4 x s8>) = G_BITCAST %0
+# GREEDY-NEXT: %1:gpr(<4 x s8>) = G_BITCAST %0
+# The greedy check is incorrect and should produce fpr.
 body:             |
   bb.0:
     liveins: $w0
 
     %0(s32) = COPY $w0
-    %1(s32) = G_BITCAST %0
+    %1(<4 x s8>) = G_BITCAST %0
 ...
 
 ---
@@ -421,20 +424,22 @@ legalized:       true
 
 # CHECK:      registers:
 # CHECK-NEXT:  - { id: 0, class: fpr, preferred-register: '' }
-# CHECK-NEXT:  - { id: 1, class: fpr, preferred-register: '' }
+# FAST-NEXT:   - { id: 1, class: gpr, preferred-register: '' }
+# GREEDY-NEXT: - { id: 1, class: fpr, preferred-register: '' }
 registers:
   - { id: 0, class: _ }
   - { id: 1, class: _ }
 
 # CHECK:  body:
 # CHECK:    %0:fpr(<2 x s16>) = COPY $s0
-# CHECK:    %1:fpr(<2 x s16>) = G_BITCAST %0
+# FAST:     %1:gpr(s32) = G_BITCAST %0
+# GREEDY:   %1:fpr(s32) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $s0
 
     %0(<2 x s16>) = COPY $s0
-    %1(<2 x s16>) = G_BITCAST %0
+    %1(s32) = G_BITCAST %0
 ...
 
 ---
@@ -490,13 +495,14 @@ registers:
   - { id: 1, class: _ }
 # CHECK:  body:
 # CHECK:    %0:gpr(s64) = COPY $x0
-# CHECK:    %1:gpr(s64) = G_BITCAST %0
+# FAST:    %1:fpr(<2 x s32>) = G_BITCAST %0
+# GREEDY:  %1:gpr(<2 x s32>) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $x0
 
     %0(s64) = COPY $x0
-    %1(s64) = G_BITCAST %0
+    %1(<2 x s32>) = G_BITCAST %0
 ...
 
 ---
@@ -508,13 +514,14 @@ registers:
   - { id: 1, class: _ }
 # CHECK:  body:
 # CHECK:    %0:fpr(<2 x s32>) = COPY $d0
-# CHECK:    %1:fpr(<2 x s32>) = G_BITCAST %0
+# FAST:     %1:gpr(s64) = G_BITCAST %0
+# GREEDY:   %1:fpr(s64) = G_BITCAST %0
 body:             |
   bb.0:
     liveins: $d0
 
     %0(<2 x s32>) = COPY $d0
-    %1(<2 x s32>) = G_BITCAST %0
+    %1(s64) = G_BITCAST %0
 ...
 
 ---

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
index 5b76737..89e310c 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-simple.mir
@@ -35,8 +35,8 @@ body:             |
   ; CHECK:   [[BITCAST:%[0-9]+]]:_(<2 x s32>) = G_BITCAST [[COPY]](s64)
   ; CHECK:   [[BITCAST1:%[0-9]+]]:_(s64) = G_BITCAST [[BITCAST]](<2 x s32>)
   ; CHECK:   $x0 = COPY [[BITCAST1]](s64)
-  ; CHECK:   [[BITCAST2:%[0-9]+]]:_(s32) = G_BITCAST [[SELECT3]](s32)
-  ; CHECK:   $w0 = COPY [[BITCAST2]](s32)
+  ; CHECK:   [[BITCAST2:%[0-9]+]]:_(<2 x s16>) = G_BITCAST [[SELECT3]](s32)
+  ; CHECK:   $w0 = COPY [[BITCAST2]](<2 x s16>)
   ; CHECK:   [[BITCAST3:%[0-9]+]]:_(<4 x s8>) = G_BITCAST [[TRUNC1]](s32)
   ; CHECK:   [[BITCAST4:%[0-9]+]]:_(s32) = G_BITCAST [[BITCAST3]](<4 x s8>)
   ; CHECK:   $w0 = COPY [[BITCAST4]](s32)
@@ -72,8 +72,8 @@ body:             |
     %12:_(<2 x s32>) = G_BITCAST %0(s64)
     %13:_(s64) = G_BITCAST %12(<2 x s32>)
     $x0 = COPY %13(s64)
-    %14:_(s32) = G_BITCAST %10(s32)
-    $w0 = COPY %14(s32)
+    %14:_(<2 x s16>) = G_BITCAST %10(s32)
+    $w0 = COPY %14
     %15:_(<4 x s8>) = G_BITCAST %4(s32)
     %20:_(s32) = G_BITCAST %15(<4 x s8>)
     $w0 = COPY %20(s32)

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
index 0846f54..d9ee37e 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-bitcast.mir
@@ -22,18 +22,21 @@ legalized:       true
 regBankSelected: true
 registers:
   - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
-
+  - { id: 1, class: fpr }
+  - { id: 2, class: gpr }
 body:             |
   bb.0:
     liveins: $w0
 
     ; CHECK-LABEL: name: bitcast_s32_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0
-    ; CHECK: $w0 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr32all = COPY [[COPY1]]
+    ; CHECK: $w0 = COPY [[COPY2]]
     %0(s32) = COPY $w0
-    %1(s32) = G_BITCAST %0
-    $w0 = COPY %1(s32)
+    %1(<2 x s16>) = G_BITCAST %0
+    %2(s32) = G_BITCAST %1
+    $w0 = COPY %2
 ...
 
 ---
@@ -43,18 +46,21 @@ regBankSelected: true
 
 registers:
   - { id: 0, class: fpr }
-  - { id: 1, class: fpr }
-
+  - { id: 1, class: gpr }
+  - { id: 2, class: fpr }
 body:             |
   bb.0:
     liveins: $s0
 
     ; CHECK-LABEL: name: bitcast_s32_fpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: $s0 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY [[COPY1]]
+    ; CHECK: $s0 = COPY [[COPY2]]
     %0(s32) = COPY $s0
-    %1(s32) = G_BITCAST %0
-    $s0 = COPY %1(s32)
+    %1(<2 x s16>) = G_BITCAST %0
+    %2(s32) = G_BITCAST %1
+    $s0 = COPY %2
 ...
 
 ---
@@ -75,8 +81,8 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY [[COPY]]
     ; CHECK: $s0 = COPY [[COPY1]]
     %0(s32) = COPY $w0
-    %1(s32) = G_BITCAST %0
-    $s0 = COPY %1(s32)
+    %1(<2 x s16>) = G_BITCAST %0
+    $s0 = COPY %1
 ...
 
 ---
@@ -94,9 +100,9 @@ body:             |
 
     ; CHECK-LABEL: name: bitcast_s32_fpr_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr32all = COPY [[COPY]]
     ; CHECK: $w0 = COPY [[COPY1]]
-    %0(s32) = COPY $s0
+    %0(<2 x s16>) = COPY $s0
     %1(s32) = G_BITCAST %0
     $w0 = COPY %1(s32)
 ...
@@ -108,7 +114,8 @@ regBankSelected: true
 
 registers:
   - { id: 0, class: gpr }
-  - { id: 1, class: gpr }
+  - { id: 1, class: fpr }
+  - { id: 2, class: gpr }
 
 body:             |
   bb.0:
@@ -116,10 +123,13 @@ body:             |
 
     ; CHECK-LABEL: name: bitcast_s64_gpr
     ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0
-    ; CHECK: $x0 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
+    ; CHECK: [[COPY2:%[0-9]+]]:gpr64 = COPY [[COPY1]]
+    ; CHECK: $x0 = COPY [[COPY2]]
     %0(s64) = COPY $x0
-    %1(s64) = G_BITCAST %0
-    $x0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    %2(s64) = G_BITCAST %1
+    $x0 = COPY %2(s64)
 ...
 
 ---
@@ -139,8 +149,8 @@ body:             |
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
     ; CHECK: $d0 = COPY [[COPY]]
     %0(s64) = COPY $d0
-    %1(s64) = G_BITCAST %0
-    $d0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    $d0 = COPY %1
 ...
 
 ---
@@ -160,8 +170,8 @@ body:             |
     ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY [[COPY]]
     ; CHECK: $d0 = COPY [[COPY1]]
     %0(s64) = COPY $x0
-    %1(s64) = G_BITCAST %0
-    $d0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    $d0 = COPY %1
 ...
 
 ---
@@ -179,11 +189,11 @@ body:             |
 
     ; CHECK-LABEL: name: bitcast_s64_fpr_gpr
     ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
-    ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY [[COPY]]
+    ; CHECK: [[COPY1:%[0-9]+]]:gpr64all = COPY [[COPY]]
     ; CHECK: $x0 = COPY [[COPY1]]
     %0(s64) = COPY $d0
-    %1(s64) = G_BITCAST %0
-    $x0 = COPY %1(s64)
+    %1(<2 x s32>) = G_BITCAST %0
+    $x0 = COPY %1
 ...
 
 ---

diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
index cda6427..36132e0 100644 (file)
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-redundant-zext.mir
@@ -93,14 +93,15 @@ body:             |
     ; CHECK-LABEL: name: dont_fold_bitcast
     ; CHECK: liveins: $w0
     ; CHECK: %copy:gpr32all = COPY $w0
-    ; CHECK: %bitcast:gpr32 = COPY %copy
-    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %bitcast, %subreg.sub_32
+    ; CHECK: %bitcast1:gpr32 = COPY %copy
+    ; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64 = SUBREG_TO_REG 0, %bitcast1, %subreg.sub_32
     ; CHECK: %zext:gpr64 = UBFMXri [[SUBREG_TO_REG]], 0, 31
     ; CHECK: $x0 = COPY %zext
     ; CHECK: RET_ReallyLR implicit $x0
     %copy:gpr(s32) = COPY $w0
-    %bitcast:gpr(s32) = G_BITCAST %copy(s32)
-    %zext:gpr(s64) = G_ZEXT %bitcast(s32)
+    %bitcast0:gpr(<4 x s8>) = G_BITCAST %copy(s32)
+    %bitcast1:gpr(s32) = G_BITCAST %bitcast0
+    %zext:gpr(s64) = G_ZEXT %bitcast1(s32)
     $x0 = COPY %zext(s64)
     RET_ReallyLR implicit $x0
 

diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
index aedcb37..6dcb28b 100644 (file)
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-bitcast.mir
@@ -11,9 +11,9 @@ body: |
     liveins: $sgpr0
     ; CHECK-LABEL: name: bitcast_s
     ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
-    ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(s32) = G_BITCAST [[COPY]](s32)
+    ; CHECK: [[BITCAST:%[0-9]+]]:sgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
     %0:_(s32) = COPY $sgpr0
-    %1:_(s32) = G_BITCAST %0
+    %1:_(<2 x s16>) = G_BITCAST %0
 ...
 
 ---
@@ -25,7 +25,7 @@ body: |
     liveins: $vgpr0
     ; CHECK-LABEL: name: bitcast_v
     ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
-    ; CHECK: [[BITCAST:%[0-9]+]]:vgpr(s32) = G_BITCAST [[COPY]](s32)
+    ; CHECK: [[BITCAST:%[0-9]+]]:vgpr(<2 x s16>) = G_BITCAST [[COPY]](s32)
     %0:_(s32) = COPY $vgpr0
-    %1:_(s32) = G_BITCAST %0
+    %1:_(<2 x s16>) = G_BITCAST %0
 ...

diff --git a/llvm/test/MachineVerifier/test_g_bitcast.mir b/llvm/test/MachineVerifier/test_g_bitcast.mir
index a399c85..24ee95b 100644 (file)
--- a/llvm/test/MachineVerifier/test_g_bitcast.mir
+++ b/llvm/test/MachineVerifier/test_g_bitcast.mir
@@ -34,4 +34,6 @@ body:             |
     %10:_(p1) = G_IMPLICIT_DEF
     %11:_(p3) = G_BITCAST %8
 
+    ; CHECK: Bad machine code: bitcast must change the type
+    %12:_(s64) = G_BITCAST %0
 ...