identify_chip(GFX1103_R1);
identify_chip(GFX1103_R2);
break;
+ case FAMILY_GFX1150:
+ identify_chip(GFX1150);
+ break;
}
- if (info->ip[AMD_IP_GFX].ver_major == 11)
+ if (info->ip[AMD_IP_GFX].ver_major == 11 && info->ip[AMD_IP_GFX].ver_minor == 5)
+ info->gfx_level = GFX11_5;
+ else if (info->ip[AMD_IP_GFX].ver_major == 11)
info->gfx_level = GFX11;
else if (info->ip[AMD_IP_GFX].ver_major == 10 && info->ip[AMD_IP_GFX].ver_minor == 3)
info->gfx_level = GFX10_3;
static bool must_wait_attr_ring(enum amd_gfx_level gfx_level, bool has_param_exports)
{
- return gfx_level == GFX11 && has_param_exports;
+ return (gfx_level == GFX11 || gfx_level == GFX11_5) && has_param_exports;
}
static void
return "GFX1103_R1";
case CHIP_GFX1103_R2:
return "GFX1103_R2";
+ case CHIP_GFX1150:
+ return "GFX1150";
default:
unreachable("Unknown GPU family");
}
case CHIP_GFX1103_R1:
case CHIP_GFX1103_R2:
return "gfx1103";
+ case CHIP_GFX1150:
+ return "gfx1150";
default:
return "";
}
CHIP_NAVI33, /* Radeon 7600, 7700S (mobile) */
CHIP_GFX1103_R1,
CHIP_GFX1103_R2,
+ CHIP_GFX1150,
CHIP_LAST,
};
GFX10,
GFX10_3,
GFX11,
+ GFX11_5,
NUM_GFX_VERSIONS,
};
si_pm4_set_reg(pm4, R_028C48_PA_SC_BINNER_CNTL_1,
S_028C48_MAX_ALLOC_COUNT(sscreen->info.pbb_max_alloc_count - 1) |
S_028C48_MAX_PRIM_PER_BATCH(1023));
+
+ if (sctx->gfx_level >= GFX11_5)
+ si_pm4_set_reg(pm4, R_028C54_PA_SC_BINNER_CNTL_2,
+ S_028C54_ENABLE_PING_PONG_BIN_ORDER(1));
+
/* Break up a pixel wave if it contains deallocs for more than
* half the parameter cache.
*