v4l2: add pinctrl support

diff --git a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
index 23e788a..73ba68b 100755 (executable)
--- a/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110-common.dtsi
@@ -73,7 +73,7 @@
        auto_calc_scl_lhcnt;
        status = "okay";
 
-       sc2235@30 {
+       sc22235: sc2235@30 {
                compatible = "sc2235";
                reg = <0x30>;
                clocks = <&clk_ext_camera>;
@@ -87,6 +87,8 @@
                sc2235-pwdn-gpios = <&gpio 15 0>;
                sc2235-esync-gpios = <&gpio 17 0>;
                sc2235-oen-gpios = <&gpio 18 0>;
+               pinctrl-names = "default";
+               pinctrl-0 = <&sc2235_pins>;
 
                port {
                        /* Parallel bus endpoint */

diff --git a/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi b/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
index 57c5629..2b85784 100644 (file)
--- a/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
+++ b/arch/riscv/boot/dts/starfive/jh7110_pinctrl.dtsi
@@ -532,3 +532,9 @@
        pinctrl-0 = <&mmc1_pins>;
        status = "okay";
 };
+
+&vin_sysctl {
+       pinctrl-names = "default";
+       pinctrl-0 = <&dvp_pins>;
+       status = "okay";        
+};

diff --git a/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c b/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
index 24204cf..4fcc3ea 100755 (executable)
--- a/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
+++ b/drivers/media/platform/starfive/v4l2_driver/stf_dvp_hw_ops.c
@@ -21,9 +21,10 @@ void stf_dvp_io_pad_config(struct stf_vin_dev *vin)
 {
        /*
         * pin: 21 ~ 35
-        * offset: 0x144 ~ 0x164
+        * iomux
         * SCFG_funcshare_pad_ctrl
         */
+#if 0
        reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x0174U, 0x1);
        reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a0U, 0x10);
        reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b4U, 0x200000);
@@ -69,7 +70,7 @@ void stf_dvp_io_pad_config(struct stf_vin_dev *vin)
        reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x01acU, 0x11);
        reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02a4U, 0x12492);
        reg_phy_write(U0_SYS_IOMUX__SAIF_BD_APBS__BASE_ADDR, 0x02b0U, 0x24924800);
-
+#endif
 }
 
 static int stf_dvp_config_set(struct stf_dvp_dev *dvp_dev)