virgl: add VIRGL_DEBUG_XFER
authorChia-I Wu <olvaffe@gmail.com>
Mon, 24 Jun 2019 17:47:59 +0000 (10:47 -0700)
committerChia-I Wu <olvaffe@gmail.com>
Tue, 25 Jun 2019 19:01:45 +0000 (12:01 -0700)
When set, do as requested and skip any transfer optimization.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-By: Gert Wollny <gert.wollny@collabora.com>
Reviewed-By: Alexandros Frantzis <alexandros.frantzis@collabora.com>
src/gallium/drivers/virgl/virgl_resource.c
src/gallium/drivers/virgl/virgl_screen.c
src/gallium/drivers/virgl/virgl_screen.h

index 0659b38..5e372de 100644 (file)
@@ -117,8 +117,9 @@ virgl_resource_transfer_prepare(struct virgl_context *vctx,
     * PIPE_TRANSFER_DISCARD_RANGE are set.
     */
    if (res->u.b.target == PIPE_BUFFER &&
-         !util_ranges_intersect(&res->valid_buffer_range, xfer->base.box.x,
-            xfer->base.box.x + xfer->base.box.width)) {
+       !util_ranges_intersect(&res->valid_buffer_range, xfer->base.box.x,
+                              xfer->base.box.x + xfer->base.box.width) &&
+       likely(!(virgl_debug & VIRGL_DEBUG_XFER))) {
       flush = false;
       readback = false;
       wait = false;
@@ -127,8 +128,10 @@ virgl_resource_transfer_prepare(struct virgl_context *vctx,
    /* When the resource is busy but its content can be discarded, we can
     * replace its HW resource or use a staging buffer to avoid waiting.
     */
-   if (wait && (xfer->base.usage & (PIPE_TRANSFER_DISCARD_RANGE |
-                                    PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE))) {
+   if (wait &&
+       (xfer->base.usage & (PIPE_TRANSFER_DISCARD_RANGE |
+                            PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE)) &&
+       likely(!(virgl_debug & VIRGL_DEBUG_XFER))) {
       bool can_realloc = false;
       bool can_staging = false;
 
index 08e7fbe..9291c97 100644 (file)
@@ -46,6 +46,7 @@ static const struct debug_named_value debug_options[] = {
    { "emubgra",   VIRGL_DEBUG_EMULATE_BGRA,        "Enable tweak to emulate BGRA as RGBA on GLES hosts"},
    { "bgraswz",   VIRGL_DEBUG_BGRA_DEST_SWIZZLE,   "Enable tweak to swizzle emulated BGRA on GLES hosts" },
    { "sync",      VIRGL_DEBUG_SYNC,                "Sync after every flush" },
+   { "xfer",      VIRGL_DEBUG_XFER,                "Do not optimize for transfers" },
    DEBUG_NAMED_VALUE_END
 };
 DEBUG_GET_ONCE_FLAGS_OPTION(virgl_debug, "VIRGL_DEBUG", debug_options, 0)
index b466c63..097bba6 100644 (file)
@@ -33,6 +33,7 @@ enum virgl_debug_flags {
    VIRGL_DEBUG_EMULATE_BGRA         = 1 << 2,
    VIRGL_DEBUG_BGRA_DEST_SWIZZLE    = 1 << 3,
    VIRGL_DEBUG_SYNC                 = 1 << 4,
+   VIRGL_DEBUG_XFER                 = 1 << 5,
 };
 
 extern int virgl_debug;