mtd: spinand: gigadevice: add support for GD5F1GQ{4,5}RExxH
authorSridharan S N <quic_sridsn@quicinc.com>
Fri, 23 Jun 2023 04:57:55 +0000 (10:27 +0530)
committerMiquel Raynal <miquel.raynal@bootlin.com>
Wed, 12 Jul 2023 11:34:27 +0000 (13:34 +0200)
Add support for:
GD5F1GQ5RExxH
GD5F1GQ4RExxH

Both are 1Gb SLC NAND flash with 4b/512b on-die ECC capability and has
2K + 64B PageSize.

Signed-off-by: Sridharan S N <quic_sridsn@quicinc.com>
Signed-off-by: Md Sadre Alam <quic_mdalam@quicinc.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lore.kernel.org/linux-mtd/20230623045757.30055-2-quic_sridsn@quicinc.com
drivers/mtd/nand/spi/gigadevice.c

index cfd7c3b..987710e 100644 (file)
@@ -511,6 +511,26 @@ static const struct spinand_info gigadevice_spinand_table[] = {
                     SPINAND_HAS_QE_BIT,
                     SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
                                     gd5fxgq4uexxg_ecc_get_status)),
+       SPINAND_INFO("GD5F1GQ5RExxH",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x21),
+                    NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+                    NAND_ECCREQ(4, 512),
+                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+                                             &write_cache_variants,
+                                             &update_cache_variants),
+                    SPINAND_HAS_QE_BIT,
+                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+                                    gd5fxgq4uexxg_ecc_get_status)),
+       SPINAND_INFO("GD5F1GQ4RExxH",
+                    SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0xc9),
+                    NAND_MEMORG(1, 2048, 64, 64, 1024, 20, 1, 1, 1),
+                    NAND_ECCREQ(4, 512),
+                    SPINAND_INFO_OP_VARIANTS(&read_cache_variants_1gq5,
+                                             &write_cache_variants,
+                                             &update_cache_variants),
+                    SPINAND_HAS_QE_BIT,
+                    SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
+                                    gd5fxgq4uexxg_ecc_get_status)),
 };
 
 static const struct spinand_manufacturer_ops gigadevice_spinand_manuf_ops = {