arm64: dts: qcom: sdm845: add SLPI remoteproc

Add the SLPI remoteproc to the SDM845 Qualcomm SoC which is responsible
for exposing the sensors connected to the SoC. The SLPI communicates
over GLink edge 'dsps' and is similar to other DSPs e.g. ADSP or CDSP.
This patch allows the SLPI to boot and expose itself over QRTR as
service 400.

Signed-off-by: Dylan Van Assche <me@dylanvanassche.be>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230406173148.28309-2-me@dylanvanassche.be

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index fe1e8b6..760da18 100644 (file)
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -3328,6 +3328,42 @@
                                      "gcc_gpu_gpll0_div_clk_src";
                };
 
+               slpi_pas: remoteproc@5c00000 {
+                       compatible = "qcom,sdm845-slpi-pas";
+                       reg = <0 0x5c00000 0 0x4000>;
+
+                       interrupts-extended = <&intc GIC_SPI 494 IRQ_TYPE_EDGE_RISING>,
+                                               <&slpi_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+                                               <&slpi_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+                                               <&slpi_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+                                               <&slpi_smp2p_in 3 IRQ_TYPE_EDGE_RISING>;
+                       interrupt-names = "wdog", "fatal", "ready",
+                                               "handover", "stop-ack";
+
+                       clocks = <&rpmhcc RPMH_CXO_CLK>;
+                       clock-names = "xo";
+
+                       qcom,qmp = <&aoss_qmp>;
+
+                       power-domains = <&rpmhpd SDM845_CX>,
+                                       <&rpmhpd SDM845_MX>;
+                       power-domain-names = "lcx", "lmx";
+
+                       memory-region = <&slpi_mem>;
+
+                       qcom,smem-states = <&slpi_smp2p_out 0>;
+                       qcom,smem-state-names = "stop";
+
+                       status = "disabled";
+
+                       glink-edge {
+                               interrupts = <GIC_SPI 170 IRQ_TYPE_EDGE_RISING>;
+                               label = "dsps";
+                               qcom,remote-pid = <3>;
+                               mboxes = <&apss_shared 24>;
+                       };
+               };
+
                stm@6002000 {
                        compatible = "arm,coresight-stm", "arm,primecell";
                        reg = <0 0x06002000 0 0x1000>,