<reg32 offset="0x0e55" name="VFD_PERFCTR_VFD_SEL_5" type="a5xx_vfd_perfcounter_select"/>
<reg32 offset="0x0e56" name="VFD_PERFCTR_VFD_SEL_6" type="a5xx_vfd_perfcounter_select"/>
<reg32 offset="0x0e57" name="VFD_PERFCTR_VFD_SEL_7" type="a5xx_vfd_perfcounter_select"/>
- <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL"/> <!-- always 00000400? -->
+ <reg32 offset="0x0e60" name="VPC_DBG_ECO_CNTL">
+ <bitfield name="ALLFLATOPTDIS" pos="10" type="boolean"/>
+ </reg32>
<reg32 offset="0x0e61" name="VPC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
<reg32 offset="0x0e62" name="VPC_MODE_CNTL">
<bitfield name="BINNING_PASS" pos="0" type="boolean"/>
<reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_3" type="a5xx_vpc_perfcounter_select"/>
<reg32 offset="0x0e80" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
+ <reg32 offset="0x0e81" name="UCHE_MODE_CNTL"/>
<reg32 offset="0x0e82" name="UCHE_SVM_CNTL"/>
<reg32 offset="0x0e87" name="UCHE_WRITE_THRU_BASE_LO"/>
<reg32 offset="0x0e88" name="UCHE_WRITE_THRU_BASE_HI"/>
<value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" varset="chip" variants="A5XX-"/>
<value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" varset="chip" variants="A5XX-"/>
<value name="CP_SET_SUBDRAW_SIZE" value="0x35" varset="chip" variants="A5XX-"/>
+ <value name="CP_WHERE_AM_I" value="0x62" varset="chip" variants="A5XX-"/>
<value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" varset="chip" variants="A5XX-"/>
<!-- Enable/Disable/Defer A5x global preemption model -->
<value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" varset="chip" variants="A5XX"/>