Add a pm function for GPU

Signed-off-by: Walker Chen <walker.chen@starfivetech.com>

diff --git a/drivers/soc/starfive/jh7110_pmu.c b/drivers/soc/starfive/jh7110_pmu.c
index 74f09b7..51380f4 100755 (executable)
--- a/drivers/soc/starfive/jh7110_pmu.c
+++ b/drivers/soc/starfive/jh7110_pmu.c
@@ -72,6 +72,19 @@ struct jh7110_pmu_data {
        unsigned int flags;
 };
 
+static void __iomem *pmu_base;
+
+static inline void pmu_writel(u32 val, u32 offset)
+{
+       writel(val, pmu_base + offset);
+}
+
+void starfive_pmu_hw_event_turn_off_mask(u32 mask)
+{
+       pmu_writel(mask, HW_EVENT_TURN_OFF_MASK);
+}
+EXPORT_SYMBOL(starfive_pmu_hw_event_turn_off_mask);
+
 static int jh7110_pmu_get_state(struct jh7110_power_dev *pmd, bool *is_on)
 {
        struct jh7110_pmu *pmu = pmd->power;
@@ -208,7 +221,7 @@ static int jh7110_pmu_probe(struct platform_device *pdev)
                return -ENOMEM;
 
        res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
-       pmu->base = devm_ioremap_resource(&pdev->dev, res);
+       pmu_base = pmu->base = devm_ioremap_resource(&pdev->dev, res);
        if (IS_ERR(pmu->base))
                return PTR_ERR(pmu->base);
 

diff --git a/include/soc/starfive/jh7110_pmu.h b/include/soc/starfive/jh7110_pmu.h
new file mode 100755 (executable)
index 0000000..47838e0
--- /dev/null
+++ b/include/soc/starfive/jh7110_pmu.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Reset driver for the StarFive JH7110 SoC
+ *
+ * Copyright (C) 2022 samin <samin.guo@starfivetech.com>
+ */
+
+#ifndef __SOC_STARFIVE_JH7110_PMU_H__
+#define __SOC_STARFIVE_JH7110_PMU_H__
+
+#include <linux/bits.h>
+#include <linux/types.h>
+
+/* SW/HW Power domain id  */
+enum PMU_POWER_DOMAIN {
+       POWER_DOMAIN_SYSTOP     = BIT(0),
+       POWER_DOMAIN_CPU        = BIT(1),
+       POWER_DOMAIN_GPUA       = BIT(2),
+       POWER_DOMAIN_VDEC       = BIT(3),
+       POWER_DOMAIN_JPU        = POWER_DOMAIN_VDEC,
+       POWER_DOMAIN_VOUT       = BIT(4),
+       POWER_DOMAIN_ISP        = BIT(5),
+       POWER_DOMAIN_VENC       = BIT(6),
+       POWER_DOMAIN_GPUB       = BIT(7),
+       POWER_DOMAIN_ALL        = GENMASK(7, 0),
+};
+
+enum PMU_HARD_EVENT {
+       PMU_HW_EVENT_RTC        = BIT(0),
+       PMU_HW_EVENT_GMAC       = BIT(1),
+       PMU_HW_EVENT_RFU        = BIT(2),
+       PMU_HW_EVENT_RGPIO0     = BIT(3),
+       PMU_HW_EVENT_RGPIO1     = BIT(4),
+       PMU_HW_EVENT_RGPIO2     = BIT(5),
+       PMU_HW_EVENT_RGPIO3     = BIT(6),
+       PMU_HW_EVENT_GPU        = BIT(7),
+       PMU_HW_EVENT_ALL        = GENMASK(7, 0),
+};
+
+/*
+ * @func: starfive_power_domain_set
+ * @dec: power domain turn-on/off by software
+ * @domain: power domain id
+ *     POWER_DOMAIN_SYSTOP:
+ *     POWER_DOMAIN_CPU
+ *     POWER_DOMAIN_GPUA
+ *     POWER_DOMAIN_VDEC
+ *     POWER_DOMAIN_VOUT
+ *     POWER_DOMAIN_ISP
+ *     POWER_DOMAIN_VENC
+ *     POWER_DOMAIN_GPUB
+ * @enable: 1:enable 0:disable
+ */
+//void starfive_power_domain_set(u32 domain, bool enable);
+
+/*
+ * @func: starfive_pmu_hw_encourage
+ * @dec: power domain turn-on/off by HW envent(interrupt)
+ * @domain: power domain id
+ * @event: Hardware trigger event. PMU_HARD_EVENT:
+       PMU_HW_EVENT_RTC,
+       PMU_HW_EVENT_GMAC,
+       PMU_HW_EVENT_RFU,
+       PMU_HW_EVENT_RGPIO0,
+       PMU_HW_EVENT_RGPIO1,
+       PMU_HW_EVENT_RGPIO2,
+       PMU_HW_EVENT_RGPIO3,
+       PMU_HW_EVENT_GPU,
+ * @enable: 1:enable 0:disable
+ *
+ * @for example:
+ *     starfive_power_domain_set_by_hwevent(POWER_DOMAIN_VDEC, RTC_EVENT, 0);
+ *
+ *     Means that when the RTC alarm is interrupted, the hardware
+ *     is triggered to close the power domain of VDEC.
+ */
+void starfive_power_domain_set_by_hwevent(u32 domain, u32 event, bool enable);
+
+/*
+ * @func: starfive_power_domain_order_on_get
+ * @dec: PMU power domian power on order get.
+ * @domian: powerff domain id
+ */
+int starfive_power_domain_order_on_get(u32 domain);
+
+/*
+ * @func: starfive_power_domain_order_off_get
+ * @dec: PMU power domian power off order get.
+ * @domian: power domain id
+ */
+int starfive_power_domain_order_off_get(u32 domain);
+
+/*
+ * @func: starfive_power_domain_order_on_set
+ * @dec: PMU power domian power on order set.
+ * @domian: powerff domain id
+ * @order: the poweron order of domain
+ */
+void starfive_power_domain_order_on_set(u32 domain, u32 order);
+
+/*
+ * @func: starfive_power_domain_order_off_set
+ * @dec: PMU power domian power off order set.
+ * @domian: power domain id
+ * @order: the poweroff order of domain
+ */
+void starfive_power_domain_order_off_set(u32 domain, u32 order);
+
+void starfive_pmu_hw_event_turn_off_mask(u32 mask);
+
+#endif /* __SOC_STARFIVE_JH7110_PMU_H__ */