In a lot of places, we were just calling `getNamedOperandIdx` to check if the result was != or == to -1.
This is fine in itself, but it's verbose and doesn't make the intention clear, IMHO. I added a `hasNamedOperand` and replaced all cases I could find with regexes and manually.
Reviewed By: arsenm, foad
Differential Revision: https://reviews.llvm.org/D137540
return true;
// Check special imm operands (used by madmk, etc)
- if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::imm) != -1) {
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::imm)) {
++NumLiterals;
LiteralSize = 4;
}
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);
if (IsGFX10Plus)
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16);
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::tfe) != -1)
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::tfe))
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
if (!IsGFX10Plus)
const int Ops[] = { AMDGPU::OpName::src0,
AMDGPU::OpName::src1,
AMDGPU::OpName::src2 };
- for (SrcNum = 0;
- SrcNum < 3 && AMDGPU::getNamedOperandIdx(Opc, Ops[SrcNum]) != -1;
- ++SrcNum);
+ for (SrcNum = 0; SrcNum < 3 && AMDGPU::hasNamedOperand(Opc, Ops[SrcNum]);
+ ++SrcNum)
+ ;
assert(SrcNum > 0);
unsigned OpSel = Inst.getOperand(OpSelIdx).getImm();
}
}
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::high) != -1) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyHigh);
- }
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::high))
+ addOptionalImmOperand(Inst, Operands, OptionalIdx,
+ AMDGPUOperand::ImmTyHigh);
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
- }
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
+ addOptionalImmOperand(Inst, Operands, OptionalIdx,
+ AMDGPUOperand::ImmTyClampSI);
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
- }
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
+ addOptionalImmOperand(Inst, Operands, OptionalIdx,
+ AMDGPUOperand::ImmTyOModSI);
}
void AMDGPUAsmParser::cvtVINTERP(MCInst &Inst, const OperandVector &Operands)
((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
}
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1) {
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers)) {
// This instruction has src modifiers
for (unsigned E = Operands.size(); I != E; ++I) {
AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
}
}
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
- }
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
+ addOptionalImmOperand(Inst, Operands, OptionalIdx,
+ AMDGPUOperand::ImmTyClampSI);
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
- }
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
+ addOptionalImmOperand(Inst, Operands, OptionalIdx,
+ AMDGPUOperand::ImmTyOModSI);
// Special case v_mac_{f16, f32} and v_fmac_{f16, f32} (gfx906/gfx10+):
// it has src2 register operand that is tied to dst operand
Inst.addOperand(Inst.getOperand(0));
}
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1) {
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)) {
assert(!IsPacked);
Inst.addOperand(Inst.getOperand(0));
}
unsigned Opc = Inst.getOpcode();
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
bool HasModifiers =
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1;
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers);
// MAC instructions are special because they have 'old'
// operand which is not tied to dst (but assumed to be).
llvm_unreachable("unhandled operand type");
}
}
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::clamp) != -1) {
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI);
- }
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::omod) != -1) {
+
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI);
- }
+
if (Desc.TSFlags & SIInstrFlags::VOP3P)
cvtVOP3P(Inst, Operands, OptionalIdx);
else if (Desc.TSFlags & SIInstrFlags::VOP3)
cvtVOP3OpSel(Inst, Operands, OptionalIdx);
- else if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
+ else if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOpSel);
}
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);
- }
+
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi))
+ addOptionalImmOperand(Inst, Operands, OptionalIdx,
+ AMDGPUOperand::ImmTyDppFi);
}
}
unsigned Opc = Inst.getOpcode();
bool HasModifiers =
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1;
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers);
unsigned I = 1;
const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppRowMask, 0xf);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBankMask, 0xf);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppBoundCtrl);
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::fi) != -1) {
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::fi)) {
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDppFi);
}
}
SkippedVcc = false;
}
- if (Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx10 &&
- Inst.getOpcode() != AMDGPU::V_NOP_sdwa_gfx9 &&
- Inst.getOpcode() != AMDGPU::V_NOP_sdwa_vi) {
+ const unsigned Opc = Inst.getOpcode();
+ if (Opc != AMDGPU::V_NOP_sdwa_gfx10 && Opc != AMDGPU::V_NOP_sdwa_gfx9 &&
+ Opc != AMDGPU::V_NOP_sdwa_vi) {
// v_nop_sdwa_sdwa_vi/gfx9 has no optional sdwa arguments
switch (BasicInstType) {
case SIInstrFlags::VOP1:
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
- AMDGPU::OpName::clamp) != -1) {
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp))
addOptionalImmOperand(Inst, Operands, OptionalIdx,
AMDGPUOperand::ImmTyClampSI, 0);
- }
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
- AMDGPU::OpName::omod) != -1) {
+
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::omod))
addOptionalImmOperand(Inst, Operands, OptionalIdx,
AMDGPUOperand::ImmTyOModSI, 0);
- }
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
- AMDGPU::OpName::dst_sel) != -1) {
+
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_sel))
addOptionalImmOperand(Inst, Operands, OptionalIdx,
AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
- }
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
- AMDGPU::OpName::dst_unused) != -1) {
+
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::dst_unused))
addOptionalImmOperand(Inst, Operands, OptionalIdx,
AMDGPUOperand::ImmTySdwaDstUnused,
DstUnused::UNUSED_PRESERVE);
- }
+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
break;
case SIInstrFlags::VOP2:
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::omod) != -1) {
+
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::omod))
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOModSI, 0);
- }
+
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstSel, SdwaSel::DWORD);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaDstUnused, DstUnused::UNUSED_PRESERVE);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
break;
case SIInstrFlags::VOPC:
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::clamp) != -1)
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::clamp))
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI, 0);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc0Sel, SdwaSel::DWORD);
addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTySdwaSrc1Sel, SdwaSel::DWORD);
DecodeStatus AMDGPUDisassembler::convertSDWAInst(MCInst &MI) const {
if (STI.getFeatureBits()[AMDGPU::FeatureGFX9] ||
STI.getFeatureBits()[AMDGPU::FeatureGFX10]) {
- if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::sdst) != -1)
+ if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::sdst))
// VOPC - insert clamp
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::clamp);
} else if (STI.getFeatureBits()[AMDGPU::FeatureVolcanicIslands]) {
if (OldIdx != -1 && Desc.getOperandConstraint(
OldIdx, MCOI::OperandConstraint::TIED_TO) == -1) {
- assert(AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2) != -1);
+ assert(AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src2));
assert(Desc.getOperandConstraint(
AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src2),
MCOI::OperandConstraint::TIED_TO) == DST_IDX);
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
auto Mods = collectVOPModifiers(MI);
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
AMDGPU::OpName::op_sel);
} else {
// Insert dummy unused src modifiers.
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::src0_modifiers);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::src1_modifiers);
}
unsigned Opc = MI.getOpcode();
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1) {
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) {
auto Mods = collectVOPModifiers(MI);
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
AMDGPU::OpName::op_sel);
assert(VDataIdx != -1);
if (BaseOpcode->BVH) {
// Add A16 operand for intersect_ray instructions
- if (AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::a16) > -1) {
+ if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::a16))
addOperand(MI, MCOperand::createImm(1));
- }
return MCDisassembler::Success;
}
auto Mods = collectVOPModifiers(MI, true);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vdst_in) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in))
insertNamedMCOperand(MI, MCOperand::createImm(0), AMDGPU::OpName::vdst_in);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel))
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSel),
AMDGPU::OpName::op_sel);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::op_sel_hi) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel_hi))
insertNamedMCOperand(MI, MCOperand::createImm(Mods.OpSelHi),
AMDGPU::OpName::op_sel_hi);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_lo) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_lo))
insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegLo),
AMDGPU::OpName::neg_lo);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::neg_hi) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::neg_hi))
insertNamedMCOperand(MI, MCOperand::createImm(Mods.NegHi),
AMDGPU::OpName::neg_hi);
unsigned DescNumOps = MCII->get(Opc).getNumOperands();
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::old) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::old))
insertNamedMCOperand(MI, MCOperand::createReg(0), AMDGPU::OpName::old);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0_modifiers) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0_modifiers))
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::src0_modifiers);
if (MI.getNumOperands() < DescNumOps &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1_modifiers) != -1)
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src1_modifiers))
insertNamedMCOperand(MI, MCOperand::createImm(0),
AMDGPU::OpName::src1_modifiers);
return MCDisassembler::Success;
(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
DPPInst.addImm(Mod0->getImm());
++NumOperands;
- } else if (AMDGPU::getNamedOperandIdx(DPPOp,
- AMDGPU::OpName::src0_modifiers) != -1) {
+ } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src0_modifiers)) {
DPPInst.addImm(0);
++NumOperands;
}
(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))));
DPPInst.addImm(Mod1->getImm());
++NumOperands;
- } else if (AMDGPU::getNamedOperandIdx(DPPOp,
- AMDGPU::OpName::src1_modifiers) != -1) {
+ } else if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::src1_modifiers)) {
DPPInst.addImm(0);
++NumOperands;
}
}
if (HasVOP3DPP) {
auto *ClampOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::clamp);
- if (ClampOpr &&
- AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::clamp) != -1) {
+ if (ClampOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::clamp)) {
DPPInst.addImm(ClampOpr->getImm());
}
auto *VdstInOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst_in);
if (VdstInOpr &&
- AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::vdst_in) != -1) {
+ AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::vdst_in)) {
DPPInst.add(*VdstInOpr);
}
auto *OmodOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::omod);
- if (OmodOpr &&
- AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::omod) != -1) {
+ if (OmodOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::omod)) {
DPPInst.addImm(OmodOpr->getImm());
}
// Validate OP_SEL has to be set to all 0 and OP_SEL_HI has to be set to
Fail = true;
break;
}
- if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel) != -1)
+ if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel))
DPPInst.addImm(OpSel);
}
if (auto *OpSelHiOpr =
Fail = true;
break;
}
- if (AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::op_sel_hi) != -1)
+ if (AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::op_sel_hi))
DPPInst.addImm(OpSelHi);
}
auto *NegOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_lo);
- if (NegOpr &&
- AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_lo) != -1) {
+ if (NegOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_lo)) {
DPPInst.addImm(NegOpr->getImm());
}
auto *NegHiOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::neg_hi);
- if (NegHiOpr &&
- AMDGPU::getNamedOperandIdx(DPPOp, AMDGPU::OpName::neg_hi) != -1) {
+ if (NegHiOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_hi)) {
DPPInst.addImm(NegHiOpr->getImm());
}
}
if (DstSel->getImm() == AMDGPU::SDWA::DWORD)
return false;
} else {
- if ((AMDGPU::getNamedOperandIdx(MI.getOpcode(),
- AMDGPU::OpName::op_sel) == -1) ||
+ if (!AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::op_sel) ||
!(TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)
->getImm() &
SISrcMods::DST_OP_SEL))
using namespace AMDGPU::VOP3PEncoding;
using namespace AMDGPU::OpName;
- if (AMDGPU::getNamedOperandIdx(Opcode, op_sel_hi) != -1) {
- if (AMDGPU::getNamedOperandIdx(Opcode, src2) != -1)
+ if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {
+ if (AMDGPU::hasNamedOperand(Opcode, src2))
return 0;
- if (AMDGPU::getNamedOperandIdx(Opcode, src1) != -1)
+ if (AMDGPU::hasNamedOperand(Opcode, src1))
return OP_SEL_HI_2;
- if (AMDGPU::getNamedOperandIdx(Opcode, src0) != -1)
+ if (AMDGPU::hasNamedOperand(Opcode, src0))
return OP_SEL_HI_1 | OP_SEL_HI_2;
}
return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;
return;
// Do not print literals from SISrc Operands for insts with mandatory literals
- int ImmLitIdx =
- AMDGPU::getNamedOperandIdx(MI.getOpcode(), AMDGPU::OpName::imm);
- if (ImmLitIdx != -1)
+ if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm))
return;
// Check for additional literals
const unsigned Opc = UseMI->getOpcode();
if (TII->isFLATScratch(*UseMI) &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) != -1 &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::saddr) == -1) {
+ AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) &&
+ !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::saddr)) {
unsigned NewOpc = AMDGPU::getFlatScratchInstSSfromSV(Opc);
UseMI->setDesc(TII->get(NewOpc));
}
if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
!TII->isGather4(Opcode) &&
- AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::dmask) != -1) {
+ AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::dmask)) {
return adjustWritemask(Node, DAG);
}
}
if (Inst.mayStore()) {
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
- AMDGPU::OpName::data0) != -1) {
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::data0)) {
setExpScore(
&Inst, TII, TRI, MRI,
AMDGPU::getNamedOperandIdx(Inst.getOpcode(), AMDGPU::OpName::data0),
CurrScore);
}
- if (AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
- AMDGPU::OpName::data1) != -1) {
+ if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::data1)) {
setExpScore(&Inst, TII, TRI, MRI,
AMDGPU::getNamedOperandIdx(Inst.getOpcode(),
AMDGPU::OpName::data1),
if (isSMRD(Opc0) && isSMRD(Opc1)) {
// Skip time and cache invalidation instructions.
- if (AMDGPU::getNamedOperandIdx(Opc0, AMDGPU::OpName::sbase) == -1 ||
- AMDGPU::getNamedOperandIdx(Opc1, AMDGPU::OpName::sbase) == -1)
+ if (!AMDGPU::hasNamedOperand(Opc0, AMDGPU::OpName::sbase) ||
+ !AMDGPU::hasNamedOperand(Opc1, AMDGPU::OpName::sbase))
return false;
unsigned NumOps = getNumOperandsNoGlue(Load0);
// The src0_modifier operand is present on all instructions
// that have modifiers.
- return AMDGPU::getNamedOperandIdx(Opcode,
- AMDGPU::OpName::src0_modifiers) != -1;
+ return AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::src0_modifiers);
}
bool SIInstrInfo::hasModifiersSet(const MachineInstr &MI,
// Add the dst operand if the 32-bit encoding also has an explicit $vdst.
// For VOPC instructions, this is replaced by an implicit def of vcc.
- if (AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::vdst) != -1) {
+ if (AMDGPU::hasNamedOperand(Op32, AMDGPU::OpName::vdst)) {
// dst
Inst32.add(MI.getOperand(0));
- } else if (AMDGPU::getNamedOperandIdx(Op32, AMDGPU::OpName::sdst) != -1) {
+ } else if (AMDGPU::hasNamedOperand(Op32, AMDGPU::OpName::sdst)) {
// VOPCX instructions won't be writing to an explicit dst, so this should
// not fail for these instructions.
assert(((MI.getOperand(0).getReg() == AMDGPU::VCC) ||
(TID.TSFlags & SIInstrFlags::DS) ? AMDGPU::OpName::data0
: AMDGPU::OpName::vdata);
if (DataIdx != -1) {
- IsAllocatable = VDstIdx != -1 ||
- AMDGPU::getNamedOperandIdx(TID.Opcode,
- AMDGPU::OpName::data1) != -1;
+ IsAllocatable = VDstIdx != -1 || AMDGPU::hasNamedOperand(
+ TID.Opcode, AMDGPU::OpName::data1);
}
}
return adjustAllocatableRegClass(ST, RI, MF.getRegInfo(), TID, RegClass,
}
if (TII.isMIMG(Opc)) {
// Ignore instructions encoded without vaddr.
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) == -1 &&
- AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0) == -1)
+ if (!AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr) &&
+ !AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr0))
return UNKNOWN;
// Ignore BVH instructions
if (AMDGPU::getMIMGBaseOpcode(Opc)->BVH)
New.add(*TII->getNamedOperand(*CI.I, AMDGPU::OpName::soffset));
// For convenience, when SGPR_IMM buffer loads are merged into a
// zero-offset load, we generate its SGPR variant.
- if (AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::offset) != -1)
+ if (AMDGPU::hasNamedOperand(Opcode, AMDGPU::OpName::offset))
New.addImm(MergedOffset);
New.addImm(CI.CPol).addMemOperand(combineKnownAdjacentMMOs(CI, Paired));
// Copy dst, if it is present in original then should also be present in SDWA
MachineOperand *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst);
if (Dst) {
- assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::vdst) != -1);
+ assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::vdst));
SDWAInst.add(*Dst);
} else if ((Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst))) {
- assert(Dst &&
- AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1);
+ assert(Dst && AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst));
SDWAInst.add(*Dst);
} else {
- assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::sdst) != -1);
+ assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::sdst));
SDWAInst.addReg(TRI->getVCC(), RegState::Define);
}
// Copy src0, initialize src0_modifiers. All sdwa instructions has src0 and
// src0_modifiers (except for v_nop_sdwa, but it can't get here)
MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0);
- assert(
- Src0 &&
- AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0) != -1 &&
- AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0_modifiers) != -1);
+ assert(Src0 && AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src0) &&
+ AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src0_modifiers));
if (auto *Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers))
SDWAInst.addImm(Mod->getImm());
else
// Copy src1 if present, initialize src1_modifiers.
MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
if (Src1) {
- assert(
- AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1) != -1 &&
- AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_modifiers) != -1);
+ assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src1) &&
+ AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src1_modifiers));
if (auto *Mod = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers))
SDWAInst.addImm(Mod->getImm());
else
}
// Copy clamp if present, initialize otherwise
- assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::clamp) != -1);
+ assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::clamp));
MachineOperand *Clamp = TII->getNamedOperand(MI, AMDGPU::OpName::clamp);
if (Clamp) {
SDWAInst.add(*Clamp);
}
// Copy omod if present, initialize otherwise if needed
- if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::omod) != -1) {
+ if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::omod)) {
MachineOperand *OMod = TII->getNamedOperand(MI, AMDGPU::OpName::omod);
if (OMod) {
SDWAInst.add(*OMod);
}
// Copy dst_sel if present, initialize otherwise if needed
- if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::dst_sel) != -1) {
+ if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_sel)) {
MachineOperand *DstSel = TII->getNamedOperand(MI, AMDGPU::OpName::dst_sel);
if (DstSel) {
SDWAInst.add(*DstSel);
}
// Copy dst_unused if present, initialize otherwise if needed
- if (AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::dst_unused) != -1) {
+ if (AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::dst_unused)) {
MachineOperand *DstUnused = TII->getNamedOperand(MI, AMDGPU::OpName::dst_unused);
if (DstUnused) {
SDWAInst.add(*DstUnused);
}
// Copy src0_sel if present, initialize otherwise
- assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src0_sel) != -1);
+ assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src0_sel));
MachineOperand *Src0Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel);
if (Src0Sel) {
SDWAInst.add(*Src0Sel);
// Copy src1_sel if present, initialize otherwise if needed
if (Src1) {
- assert(AMDGPU::getNamedOperandIdx(SDWAOpcode, AMDGPU::OpName::src1_sel) != -1);
+ assert(AMDGPU::hasNamedOperand(SDWAOpcode, AMDGPU::OpName::src1_sel));
MachineOperand *Src1Sel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel);
if (Src1Sel) {
SDWAInst.add(*Src1Sel);
unsigned LoadStoreOp,
unsigned EltSize) {
bool IsStore = TII->get(LoadStoreOp).mayStore();
- bool HasVAddr = AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::vaddr) != -1;
+ bool HasVAddr = AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::vaddr);
bool UseST =
- !HasVAddr &&
- AMDGPU::getNamedOperandIdx(LoadStoreOp, AMDGPU::OpName::saddr) < 0;
+ !HasVAddr && !AMDGPU::hasNamedOperand(LoadStoreOp, AMDGPU::OpName::saddr);
switch (EltSize) {
case 4:
if (!Offset) {
unsigned Opc = MI->getOpcode();
int NewOpc = -1;
- if (AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr) != -1) {
+ if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vaddr)) {
NewOpc = AMDGPU::getFlatScratchInstSVfromSVS(Opc);
} else if (ST.hasFlatScratchSTMode()) {
// On GFX10 we have ST mode to use no registers for an address.
}
bool isVOPD(unsigned Opc) {
- return AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src0X) != -1;
+ return AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::src0X);
}
bool isTrue16Inst(unsigned Opc) {
int16_t getNamedOperandIdx(uint16_t Opcode, uint16_t NamedIdx);
LLVM_READONLY
+inline bool hasNamedOperand(uint64_t Opcode, uint64_t NamedIdx) {
+ return getNamedOperandIdx(Opcode, NamedIdx) != -1;
+}
+
+LLVM_READONLY
int getSOPPWithRelaxation(uint16_t Opcode);
struct MIMGBaseOpcodeInfo {