asahi: Do not support masking with spilled RTs

Extra complexity for this interaction, not worth it until we have an actual use
case IMHO.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24258>

diff --git a/src/asahi/lib/agx_tilebuffer.c b/src/asahi/lib/agx_tilebuffer.c
index c427462..9b83801 100644 (file)
--- a/src/asahi/lib/agx_tilebuffer.c
+++ b/src/asahi/lib/agx_tilebuffer.c
@@ -123,6 +123,12 @@ agx_tilebuffer_physical_format(struct agx_tilebuffer_layout *tib, unsigned rt)
 bool
 agx_tilebuffer_supports_mask(struct agx_tilebuffer_layout *tib, unsigned rt)
 {
+   /* We don't bother support masking with spilled render targets. This might be
+    * optimized in the future but spilling is so rare anyway it's not worth it.
+    */
+   if (tib->spilled[rt])
+      return false;
+
    enum pipe_format fmt = agx_tilebuffer_physical_format(tib, rt);
    return agx_internal_format_supports_mask((enum agx_internal_formats)fmt);
 }