drm/i915: distinguish G33 and Pineview from each other

Pineview deserves to use its own platform enum (which was already added,
unused, previously). IS_G33() no longer matches Pineview, and gets
replaced by IS_G33() || IS_PINEVIEW() or equivalent. Pineview is no
longer an outlier among platform definitions.

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1481143689-19672-1-git-send-email-jani.nikula@intel.com

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b9138cd..1480e73 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -772,7 +772,6 @@ struct intel_csr {
 
 #define DEV_INFO_FOR_EACH_FLAG(func) \
        func(is_mobile); \
-       func(is_pineview); \
        func(is_lp); \
        func(is_alpha_support); \
        /* Keep has_* in alphabetical order */ \
@@ -2619,7 +2618,7 @@ intel_info(const struct drm_i915_private *dev_priv)
 #define IS_G4X(dev_priv)       (IS_G45(dev_priv) || IS_GM45(dev_priv))
 #define IS_PINEVIEW_G(dev_priv)        (INTEL_DEVID(dev_priv) == 0xa001)
 #define IS_PINEVIEW_M(dev_priv)        (INTEL_DEVID(dev_priv) == 0xa011)
-#define IS_PINEVIEW(dev_priv)  ((dev_priv)->info.is_pineview)
+#define IS_PINEVIEW(dev_priv)  ((dev_priv)->info.platform == INTEL_PINEVIEW)
 #define IS_G33(dev_priv)       ((dev_priv)->info.platform == INTEL_G33)
 #define IS_IRONLAKE_M(dev_priv)        (INTEL_DEVID(dev_priv) == 0x0046)
 #define IS_IVYBRIDGE(dev_priv) ((dev_priv)->info.platform == INTEL_IVYBRIDGE)

diff --git a/drivers/gpu/drm/i915/i915_gem.c b/drivers/gpu/drm/i915/i915_gem.c
index dd1a34a..3618394 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem.c
+++ b/drivers/gpu/drm/i915/i915_gem.c
@@ -2084,7 +2084,8 @@ u64 i915_gem_get_ggtt_alignment(struct drm_i915_private *dev_priv, u64 size,
         * Minimum alignment is 4k (GTT page size), but might be greater
         * if a fence register is needed for the object.
         */
-       if (INTEL_GEN(dev_priv) >= 4 || (!fenced && IS_G33(dev_priv)) ||
+       if (INTEL_GEN(dev_priv) >= 4 ||
+           (!fenced && (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))) ||
            tiling_mode == I915_TILING_NONE)
                return 4096;
 
@@ -4498,8 +4499,9 @@ i915_gem_load_init_fences(struct drm_i915_private *dev_priv)
        if (INTEL_INFO(dev_priv)->gen >= 7 && !IS_VALLEYVIEW(dev_priv) &&
            !IS_CHERRYVIEW(dev_priv))
                dev_priv->num_fence_regs = 32;
-       else if (INTEL_INFO(dev_priv)->gen >= 4 || IS_I945G(dev_priv) ||
-                IS_I945GM(dev_priv) || IS_G33(dev_priv))
+       else if (INTEL_INFO(dev_priv)->gen >= 4 ||
+                IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
+                IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
                dev_priv->num_fence_regs = 16;
        else
                dev_priv->num_fence_regs = 8;

diff --git a/drivers/gpu/drm/i915/i915_gem_fence_reg.c b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
index d006bcb..09193cf 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_fence_reg.c
+++ b/drivers/gpu/drm/i915/i915_gem_fence_reg.c
@@ -512,8 +512,9 @@ i915_gem_detect_bit_6_swizzle(struct drm_i915_private *dev_priv)
                 */
                swizzle_x = I915_BIT_6_SWIZZLE_NONE;
                swizzle_y = I915_BIT_6_SWIZZLE_NONE;
-       } else if (IS_MOBILE(dev_priv) || (IS_GEN3(dev_priv) &&
-                  !IS_G33(dev_priv))) {
+       } else if (IS_MOBILE(dev_priv) ||
+                  (IS_GEN3(dev_priv) &&
+                   !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv))) {
                uint32_t dcc;
 
                /* On 9xx chipsets, channel interleave by the CPU is

diff --git a/drivers/gpu/drm/i915/i915_gem_stolen.c b/drivers/gpu/drm/i915/i915_gem_stolen.c
index c81b22f..efc0e74 100644 (file)
--- a/drivers/gpu/drm/i915/i915_gem_stolen.c
+++ b/drivers/gpu/drm/i915/i915_gem_stolen.c
@@ -203,8 +203,8 @@ static unsigned long i915_stolen_to_physical(struct drm_i915_private *dev_priv)
                return 0;
 
        /* make sure we don't clobber the GTT if it's within stolen memory */
-       if (INTEL_GEN(dev_priv) <= 4 && !IS_G33(dev_priv) &&
-           !IS_G4X(dev_priv)) {
+       if (INTEL_GEN(dev_priv) <= 4 &&
+           !IS_G33(dev_priv) && !IS_PINEVIEW(dev_priv) && !IS_G4X(dev_priv)) {
                struct {
                        u32 start, end;
                } stolen[2] = {

diff --git a/drivers/gpu/drm/i915/i915_pci.c b/drivers/gpu/drm/i915/i915_pci.c
index f7ec6e9..93f50ef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_pci.c
+++ b/drivers/gpu/drm/i915/i915_pci.c
@@ -141,7 +141,7 @@ static const struct intel_device_info intel_g33_info = {
 
 static const struct intel_device_info intel_pineview_info = {
        GEN3_FEATURES,
-       .platform = INTEL_G33, .is_pineview = 1, .is_mobile = 1,
+       .platform = INTEL_PINEVIEW, .is_mobile = 1,
        .has_hotplug = 1,
        .has_overlay = 1,
 };

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index a41082e..9eaf1e5 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -8180,7 +8180,8 @@ static void i9xx_compute_dpll(struct intel_crtc *crtc,
        else
                dpll |= DPLLB_MODE_DAC_SERIAL;
 
-       if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || IS_G33(dev_priv)) {
+       if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
+           IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
                dpll |= (crtc_state->pixel_multiplier - 1)
                        << SDVO_MULTIPLIER_SHIFT_HIRES;
        }
@@ -8893,7 +8894,7 @@ static bool i9xx_get_pipe_config(struct intel_crtc *crtc,
                         >> DPLL_MD_UDI_MULTIPLIER_SHIFT) + 1;
                pipe_config->dpll_hw_state.dpll_md = tmp;
        } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
-                  IS_G33(dev_priv)) {
+                  IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
                tmp = I915_READ(DPLL(crtc->pipe));
                pipe_config->pixel_multiplier =
                        ((tmp & SDVO_MULTIPLIER_MASK)

diff --git a/drivers/gpu/drm/i915/intel_sdvo.c b/drivers/gpu/drm/i915/intel_sdvo.c
index 054acd9..2ad1390 100644 (file)
--- a/drivers/gpu/drm/i915/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/intel_sdvo.c
@@ -1296,7 +1296,7 @@ static void intel_sdvo_pre_enable(struct intel_encoder *intel_encoder,
        if (INTEL_GEN(dev_priv) >= 4) {
                /* done in crtc_mode_set as the dpll_md reg must be written early */
        } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) ||
-                  IS_G33(dev_priv)) {
+                  IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) {
                /* done in crtc_mode_set as it lives inside the dpll register */
        } else {
                sdvox |= (crtc_state->pixel_multiplier - 1)

diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c
index 07779d0..2007b13 100644 (file)
--- a/drivers/gpu/drm/i915/intel_uncore.c
+++ b/drivers/gpu/drm/i915/intel_uncore.c
@@ -1812,7 +1812,7 @@ static reset_func intel_get_gpu_reset(struct drm_i915_private *dev_priv)
                return ironlake_do_reset;
        else if (IS_G4X(dev_priv))
                return g4x_do_reset;
-       else if (IS_G33(dev_priv))
+       else if (IS_G33(dev_priv) || IS_PINEVIEW(dev_priv))
                return g33_do_reset;
        else if (INTEL_INFO(dev_priv)->gen >= 3)
                return i915_do_reset;