Merge branch 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind...

* 'omap-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap-2.6: (47 commits)
  OMAP clock: use debugfs_remove_recursive() for rewinding
  OMAP2/3/4 core: create omap_device layer
  OMAP: omap_hwmod: call omap_hwmod init at boot; create interconnects
  OMAP2/3/4: create omap_hwmod layer
  OMAP2/3 board-*.c files: read bootloader configuration earlier
  OMAP2/3/4 PRCM: add module IDLEST wait code
  OMAP2/3 PM: create the OMAP PM interface and add a default OMAP PM no-op layer
  OMAP3 clock: remove superfluous calls to omap2_init_clk_clkdm
  OMAP clock: associate MPU clocks with the mpu_clkdm
  OMAP3 clock: Fixed processing of bootarg 'mpurate'
  OMAP: SDRC: Add several new register definitions
  OMAP: powerdomain: Fix overflow when doing powerdomain deps lookups.
  OMAP: PM: Added suspend target state control to debugfs for OMAP3
  OMAP: PM debug: Add PRCM register dump support
  OMAP: PM debug: make powerdomains use PM-debug counters
  OMAP: PM: Add pm-debug counters
  OMAP: PM: Add closures to clkdm_for_each and pwrdm_for_each.
  OMAP: PM: Hook into PM counters
  OMAP: PM counter infrastructure.
  OMAP3: PM: fix lockdep warning caused by omap3_pm_init
  ...

diff --combined arch/arm/mach-omap2/board-4430sdp.c
index 1b22307,f22f429..eb37c40
--- 1/arch/arm/mach-omap2/board-4430sdp.c
--- 2/arch/arm/mach-omap2/board-4430sdp.c
+++ b/arch/arm/mach-omap2/board-4430sdp.c
@@@ -39,7 -39,7 +39,7 @@@ static struct platform_device *sdp4430_
  };
  
  static struct omap_uart_config sdp4430_uart_config __initdata = {
 -      .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2),
 +      .enabled_uarts  = (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3),
  };
  
  static struct omap_lcd_config sdp4430_lcd_config __initdata = {
@@@ -47,14 -47,13 +47,13 @@@
  };
  
  static struct omap_board_config_kernel sdp4430_config[] __initdata = {
-       { OMAP_TAG_UART,        &sdp4430_uart_config },
        { OMAP_TAG_LCD,         &sdp4430_lcd_config },
  };
  
  static void __init gic_init_irq(void)
  {
-       gic_dist_init(0, IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
-       gic_cpu_init(0, IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
+       gic_dist_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_DIST_BASE), 29);
+       gic_cpu_init(0, OMAP2_IO_ADDRESS(OMAP44XX_GIC_CPU_BASE));
  }
  
  static void __init omap_4430sdp_init_irq(void)

diff --combined arch/arm/mach-omap2/serial.c
index ce22344,021130d..3a529c7
--- 1/arch/arm/mach-omap2/serial.c
--- 2/arch/arm/mach-omap2/serial.c
+++ b/arch/arm/mach-omap2/serial.c
@@@ -73,7 -73,7 +73,7 @@@ static LIST_HEAD(uart_list)
  
  static struct plat_serial8250_port serial_platform_data0[] = {
        {
-               .membase        = IO_ADDRESS(OMAP_UART1_BASE),
+               .membase        = OMAP2_IO_ADDRESS(OMAP_UART1_BASE),
                .mapbase        = OMAP_UART1_BASE,
                .irq            = 72,
                .flags          = UPF_BOOT_AUTOCONF,
@@@ -87,7 -87,7 +87,7 @@@
  
  static struct plat_serial8250_port serial_platform_data1[] = {
        {
-               .membase        = IO_ADDRESS(OMAP_UART2_BASE),
+               .membase        = OMAP2_IO_ADDRESS(OMAP_UART2_BASE),
                .mapbase        = OMAP_UART2_BASE,
                .irq            = 73,
                .flags          = UPF_BOOT_AUTOCONF,
@@@ -101,7 -101,7 +101,7 @@@
  
  static struct plat_serial8250_port serial_platform_data2[] = {
        {
-               .membase        = IO_ADDRESS(OMAP_UART3_BASE),
+               .membase        = OMAP2_IO_ADDRESS(OMAP_UART3_BASE),
                .mapbase        = OMAP_UART3_BASE,
                .irq            = 74,
                .flags          = UPF_BOOT_AUTOCONF,
@@@ -109,20 -109,25 +109,35 @@@
                .regshift       = 2,
                .uartclk        = OMAP24XX_BASE_BAUD * 16,
        }, {
 +#ifdef CONFIG_ARCH_OMAP4
 +              .membase        = IO_ADDRESS(OMAP_UART4_BASE),
 +              .mapbase        = OMAP_UART4_BASE,
 +              .irq            = 70,
 +              .flags          = UPF_BOOT_AUTOCONF,
 +              .iotype         = UPIO_MEM,
 +              .regshift       = 2,
 +              .uartclk        = OMAP24XX_BASE_BAUD * 16,
 +      }, {
 +#endif
                .flags          = 0
        }
  };
  
+ #ifdef CONFIG_ARCH_OMAP4
+ static struct plat_serial8250_port serial_platform_data3[] = {
+       {
+               .membase        = IO_ADDRESS(OMAP_UART4_BASE),
+               .mapbase        = OMAP_UART4_BASE,
+               .irq            = 70,
+               .flags          = UPF_BOOT_AUTOCONF,
+               .iotype         = UPIO_MEM,
+               .regshift       = 2,
+               .uartclk        = OMAP24XX_BASE_BAUD * 16,
+       }, {
+               .flags          = 0
+       }
+ };
+ #endif
  static inline unsigned int serial_read_reg(struct plat_serial8250_port *up,
                                           int offset)
  {
@@@ -470,7 -475,7 +485,7 @@@ static void omap_uart_idle_init(struct 
                uart->padconf = 0;
        }
  
-       p->flags |= UPF_SHARE_IRQ;
+       p->irqflags |= IRQF_SHARED;
        ret = request_irq(p->irq, omap_uart_interrupt, IRQF_SHARED,
                          "serial idle", (void *)uart);
        WARN_ON(ret);
@@@ -560,12 -565,22 +575,22 @@@ static struct omap_uart_state omap_uart
                        },
                },
        },
+ #ifdef CONFIG_ARCH_OMAP4
+       {
+               .pdev = {
+                       .name                   = "serial8250",
+                       .id                     = 3
+                       .dev                    = {
+                               .platform_data  = serial_platform_data3,
+                       },
+               },
+       },
+ #endif
  };
  
- void __init omap_serial_init(void)
+ void __init omap_serial_early_init(void)
  {
        int i;
-       const struct omap_uart_config *info;
        char name[16];
  
        /*
@@@ -574,23 -589,12 +599,12 @@@
         * if not needed.
         */
  
-       info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
- 
-       if (info == NULL)
-               return;
- 
        for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
                struct omap_uart_state *uart = &omap_uart[i];
                struct platform_device *pdev = &uart->pdev;
                struct device *dev = &pdev->dev;
                struct plat_serial8250_port *p = dev->platform_data;
  
-               if (!(info->enabled_uarts & (1 << i))) {
-                       p->membase = NULL;
-                       p->mapbase = 0;
-                       continue;
-               }
- 
                sprintf(name, "uart%d_ick", i+1);
                uart->ick = clk_get(NULL, name);
                if (IS_ERR(uart->ick)) {
@@@ -605,8 -609,11 +619,11 @@@
                        uart->fck = NULL;
                }
  
-               if (!uart->ick || !uart->fck)
-                       continue;
+               /* FIXME: Remove this once the clkdev is ready */
+               if (!cpu_is_omap44xx()) {
+                       if (!uart->ick || !uart->fck)
+                               continue;
+               }
  
                uart->num = i;
                p->private_data = uart;
@@@ -617,6 -624,18 +634,18 @@@
                        p->irq += 32;
  
                omap_uart_enable_clocks(uart);
+       }
+ }
+ 
+ void __init omap_serial_init(void)
+ {
+       int i;
+ 
+       for (i = 0; i < OMAP_MAX_NR_PORTS; i++) {
+               struct omap_uart_state *uart = &omap_uart[i];
+               struct platform_device *pdev = &uart->pdev;
+               struct device *dev = &pdev->dev;
+ 
                omap_uart_reset(uart);
                omap_uart_idle_init(uart);
  

diff --combined arch/arm/plat-omap/common.c
index 95587b6,a6fa786..3a4768d
--- 1/arch/arm/plat-omap/common.c
--- 2/arch/arm/plat-omap/common.c
+++ b/arch/arm/plat-omap/common.c
@@@ -54,50 -54,6 +54,6 @@@ static const void *get_config(u16 tag, 
        struct omap_board_config_kernel *kinfo = NULL;
        int i;
  
- #ifdef CONFIG_OMAP_BOOT_TAG
-       struct omap_board_config_entry *info = NULL;
- 
-       if (omap_bootloader_tag_len > 4)
-               info = (struct omap_board_config_entry *) omap_bootloader_tag;
-       while (info != NULL) {
-               u8 *next;
- 
-               if (info->tag == tag) {
-                       if (skip == 0)
-                               break;
-                       skip--;
-               }
- 
-               if ((info->len & 0x03) != 0) {
-                       /* We bail out to avoid an alignment fault */
-                       printk(KERN_ERR "OMAP peripheral config: Length (%d) not word-aligned (tag %04x)\n",
-                              info->len, info->tag);
-                       return NULL;
-               }
-               next = (u8 *) info + sizeof(*info) + info->len;
-               if (next >= omap_bootloader_tag + omap_bootloader_tag_len)
-                       info = NULL;
-               else
-                       info = (struct omap_board_config_entry *) next;
-       }
-       if (info != NULL) {
-               /* Check the length as a lame attempt to check for
-                * binary inconsistency. */
-               if (len != NO_LENGTH_CHECK) {
-                       /* Word-align len */
-                       if (len & 0x03)
-                               len = (len + 3) & ~0x03;
-                       if (info->len != len) {
-                               printk(KERN_ERR "OMAP peripheral config: Length mismatch with tag %x (want %d, got %d)\n",
-                                      tag, len, info->len);
-                               return NULL;
-                       }
-               }
-               if (len_out != NULL)
-                       *len_out = info->len;
-               return info->data;
-       }
- #endif
        /* Try to find the config from the board-specific structures
         * in the kernel. */
        for (i = 0; i < omap_board_config_size; i++) {
@@@ -127,50 -83,6 +83,6 @@@ const void *omap_get_var_config(u16 tag
  }
  EXPORT_SYMBOL(omap_get_var_config);
  
- static int __init omap_add_serial_console(void)
- {
-       const struct omap_serial_console_config *con_info;
-       const struct omap_uart_config *uart_info;
-       static char speed[11], *opt = NULL;
-       int line, i, uart_idx;
- 
-       uart_info = omap_get_config(OMAP_TAG_UART, struct omap_uart_config);
-       con_info = omap_get_config(OMAP_TAG_SERIAL_CONSOLE,
-                                       struct omap_serial_console_config);
-       if (uart_info == NULL || con_info == NULL)
-               return 0;
- 
-       if (con_info->console_uart == 0)
-               return 0;
- 
-       if (con_info->console_speed) {
-               snprintf(speed, sizeof(speed), "%u", con_info->console_speed);
-               opt = speed;
-       }
- 
-       uart_idx = con_info->console_uart - 1;
-       if (uart_idx >= OMAP_MAX_NR_PORTS) {
-               printk(KERN_INFO "Console: external UART#%d. "
-                       "Not adding it as console this time.\n",
-                       uart_idx + 1);
-               return 0;
-       }
-       if (!(uart_info->enabled_uarts & (1 << uart_idx))) {
-               printk(KERN_ERR "Console: Selected UART#%d is "
-                       "not enabled for this platform\n",
-                       uart_idx + 1);
-               return -1;
-       }
-       line = 0;
-       for (i = 0; i < uart_idx; i++) {
-               if (uart_info->enabled_uarts & (1 << i))
-                       line++;
-       }
-       return add_preferred_console("ttyS", line, opt);
- }
- console_initcall(omap_add_serial_console);
- 
- 
  /*
   * 32KHz clocksource ... always available, on pretty most chips except
   * OMAP 730 and 1510.  Other timers could be used as clocksources, with
@@@ -253,8 -165,11 +165,8 @@@ static struct clocksource clocksource_3
   */
  unsigned long long sched_clock(void)
  {
 -      unsigned long long ret;
 -
 -      ret = (unsigned long long)clocksource_32k.read(&clocksource_32k);
 -      ret = (ret * clocksource_32k.mult_orig) >> clocksource_32k.shift;
 -      return ret;
 +      return clocksource_cyc2ns(clocksource_32k.read(&clocksource_32k),
 +                                clocksource_32k.mult, clocksource_32k.shift);
  }
  
  static int __init omap_init_clocksource_32k(void)

diff --combined arch/arm/plat-omap/dma.c
index 9b00f4c,bf08634..fd3154a
--- 1/arch/arm/plat-omap/dma.c
--- 2/arch/arm/plat-omap/dma.c
+++ b/arch/arm/plat-omap/dma.c
@@@ -1127,11 -1127,6 +1127,11 @@@ int omap_dma_running(void
  void omap_dma_link_lch(int lch_head, int lch_queue)
  {
        if (omap_dma_in_1510_mode()) {
 +              if (lch_head == lch_queue) {
 +                      dma_write(dma_read(CCR(lch_head)) | (3 << 8),
 +                                                              CCR(lch_head));
 +                      return;
 +              }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
                BUG();
                return;
@@@ -1154,11 -1149,6 +1154,11 @@@ EXPORT_SYMBOL(omap_dma_link_lch)
  void omap_dma_unlink_lch(int lch_head, int lch_queue)
  {
        if (omap_dma_in_1510_mode()) {
 +              if (lch_head == lch_queue) {
 +                      dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
 +                                                              CCR(lch_head));
 +                      return;
 +              }
                printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
                BUG();
                return;
@@@ -2347,16 -2337,16 +2347,16 @@@ static int __init omap_init_dma(void
        int ch, r;
  
        if (cpu_class_is_omap1()) {
-               omap_dma_base = IO_ADDRESS(OMAP1_DMA_BASE);
+               omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
                dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
        } else if (cpu_is_omap24xx()) {
-               omap_dma_base = IO_ADDRESS(OMAP24XX_DMA4_BASE);
+               omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
        } else if (cpu_is_omap34xx()) {
-               omap_dma_base = IO_ADDRESS(OMAP34XX_DMA4_BASE);
+               omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
        } else if (cpu_is_omap44xx()) {
-               omap_dma_base = IO_ADDRESS(OMAP44XX_DMA4_BASE);
+               omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
                dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
        } else {
                pr_err("DMA init failed for unsupported omap\n");

diff --combined arch/arm/plat-omap/gpio.c
index 176c86e,7c70a6a..693839c
--- 1/arch/arm/plat-omap/gpio.c
--- 2/arch/arm/plat-omap/gpio.c
+++ b/arch/arm/plat-omap/gpio.c
@@@ -31,7 -31,7 +31,7 @@@
  /*
   * OMAP1510 GPIO registers
   */
- #define OMAP1510_GPIO_BASE            IO_ADDRESS(0xfffce000)
+ #define OMAP1510_GPIO_BASE            OMAP1_IO_ADDRESS(0xfffce000)
  #define OMAP1510_GPIO_DATA_INPUT      0x00
  #define OMAP1510_GPIO_DATA_OUTPUT     0x04
  #define OMAP1510_GPIO_DIR_CONTROL     0x08
@@@ -45,10 -45,10 +45,10 @@@
  /*
   * OMAP1610 specific GPIO registers
   */
- #define OMAP1610_GPIO1_BASE           IO_ADDRESS(0xfffbe400)
- #define OMAP1610_GPIO2_BASE           IO_ADDRESS(0xfffbec00)
- #define OMAP1610_GPIO3_BASE           IO_ADDRESS(0xfffbb400)
- #define OMAP1610_GPIO4_BASE           IO_ADDRESS(0xfffbbc00)
+ #define OMAP1610_GPIO1_BASE           OMAP1_IO_ADDRESS(0xfffbe400)
+ #define OMAP1610_GPIO2_BASE           OMAP1_IO_ADDRESS(0xfffbec00)
+ #define OMAP1610_GPIO3_BASE           OMAP1_IO_ADDRESS(0xfffbb400)
+ #define OMAP1610_GPIO4_BASE           OMAP1_IO_ADDRESS(0xfffbbc00)
  #define OMAP1610_GPIO_REVISION                0x0000
  #define OMAP1610_GPIO_SYSCONFIG               0x0010
  #define OMAP1610_GPIO_SYSSTATUS               0x0014
@@@ -70,12 -70,12 +70,12 @@@
  /*
   * OMAP730 specific GPIO registers
   */
- #define OMAP730_GPIO1_BASE            IO_ADDRESS(0xfffbc000)
- #define OMAP730_GPIO2_BASE            IO_ADDRESS(0xfffbc800)
- #define OMAP730_GPIO3_BASE            IO_ADDRESS(0xfffbd000)
- #define OMAP730_GPIO4_BASE            IO_ADDRESS(0xfffbd800)
- #define OMAP730_GPIO5_BASE            IO_ADDRESS(0xfffbe000)
- #define OMAP730_GPIO6_BASE            IO_ADDRESS(0xfffbe800)
+ #define OMAP730_GPIO1_BASE            OMAP1_IO_ADDRESS(0xfffbc000)
+ #define OMAP730_GPIO2_BASE            OMAP1_IO_ADDRESS(0xfffbc800)
+ #define OMAP730_GPIO3_BASE            OMAP1_IO_ADDRESS(0xfffbd000)
+ #define OMAP730_GPIO4_BASE            OMAP1_IO_ADDRESS(0xfffbd800)
+ #define OMAP730_GPIO5_BASE            OMAP1_IO_ADDRESS(0xfffbe000)
+ #define OMAP730_GPIO6_BASE            OMAP1_IO_ADDRESS(0xfffbe800)
  #define OMAP730_GPIO_DATA_INPUT               0x00
  #define OMAP730_GPIO_DATA_OUTPUT      0x04
  #define OMAP730_GPIO_DIR_CONTROL      0x08
@@@ -86,12 -86,12 +86,12 @@@
  /*
   * OMAP850 specific GPIO registers
   */
- #define OMAP850_GPIO1_BASE            IO_ADDRESS(0xfffbc000)
- #define OMAP850_GPIO2_BASE            IO_ADDRESS(0xfffbc800)
- #define OMAP850_GPIO3_BASE            IO_ADDRESS(0xfffbd000)
- #define OMAP850_GPIO4_BASE            IO_ADDRESS(0xfffbd800)
- #define OMAP850_GPIO5_BASE            IO_ADDRESS(0xfffbe000)
- #define OMAP850_GPIO6_BASE            IO_ADDRESS(0xfffbe800)
+ #define OMAP850_GPIO1_BASE            OMAP1_IO_ADDRESS(0xfffbc000)
+ #define OMAP850_GPIO2_BASE            OMAP1_IO_ADDRESS(0xfffbc800)
+ #define OMAP850_GPIO3_BASE            OMAP1_IO_ADDRESS(0xfffbd000)
+ #define OMAP850_GPIO4_BASE            OMAP1_IO_ADDRESS(0xfffbd800)
+ #define OMAP850_GPIO5_BASE            OMAP1_IO_ADDRESS(0xfffbe000)
+ #define OMAP850_GPIO6_BASE            OMAP1_IO_ADDRESS(0xfffbe800)
  #define OMAP850_GPIO_DATA_INPUT               0x00
  #define OMAP850_GPIO_DATA_OUTPUT      0x04
  #define OMAP850_GPIO_DIR_CONTROL      0x08
@@@ -99,19 -99,21 +99,21 @@@
  #define OMAP850_GPIO_INT_MASK         0x10
  #define OMAP850_GPIO_INT_STATUS               0x14
  
+ #define OMAP1_MPUIO_VBASE             OMAP1_IO_ADDRESS(OMAP1_MPUIO_BASE)
+ 
  /*
   * omap24xx specific GPIO registers
   */
- #define OMAP242X_GPIO1_BASE           IO_ADDRESS(0x48018000)
- #define OMAP242X_GPIO2_BASE           IO_ADDRESS(0x4801a000)
- #define OMAP242X_GPIO3_BASE           IO_ADDRESS(0x4801c000)
- #define OMAP242X_GPIO4_BASE           IO_ADDRESS(0x4801e000)
+ #define OMAP242X_GPIO1_BASE           OMAP2_IO_ADDRESS(0x48018000)
+ #define OMAP242X_GPIO2_BASE           OMAP2_IO_ADDRESS(0x4801a000)
+ #define OMAP242X_GPIO3_BASE           OMAP2_IO_ADDRESS(0x4801c000)
+ #define OMAP242X_GPIO4_BASE           OMAP2_IO_ADDRESS(0x4801e000)
  
- #define OMAP243X_GPIO1_BASE           IO_ADDRESS(0x4900C000)
- #define OMAP243X_GPIO2_BASE           IO_ADDRESS(0x4900E000)
- #define OMAP243X_GPIO3_BASE           IO_ADDRESS(0x49010000)
- #define OMAP243X_GPIO4_BASE           IO_ADDRESS(0x49012000)
- #define OMAP243X_GPIO5_BASE           IO_ADDRESS(0x480B6000)
+ #define OMAP243X_GPIO1_BASE           OMAP2_IO_ADDRESS(0x4900C000)
+ #define OMAP243X_GPIO2_BASE           OMAP2_IO_ADDRESS(0x4900E000)
+ #define OMAP243X_GPIO3_BASE           OMAP2_IO_ADDRESS(0x49010000)
+ #define OMAP243X_GPIO4_BASE           OMAP2_IO_ADDRESS(0x49012000)
+ #define OMAP243X_GPIO5_BASE           OMAP2_IO_ADDRESS(0x480B6000)
  
  #define OMAP24XX_GPIO_REVISION                0x0000
  #define OMAP24XX_GPIO_SYSCONFIG               0x0010
@@@ -138,54 -140,26 +140,52 @@@
  #define OMAP24XX_GPIO_CLEARDATAOUT    0x0090
  #define OMAP24XX_GPIO_SETDATAOUT      0x0094
  
 +#define OMAP4_GPIO_REVISION           0x0000
 +#define OMAP4_GPIO_SYSCONFIG          0x0010
 +#define OMAP4_GPIO_EOI                        0x0020
 +#define OMAP4_GPIO_IRQSTATUSRAW0      0x0024
 +#define OMAP4_GPIO_IRQSTATUSRAW1      0x0028
 +#define OMAP4_GPIO_IRQSTATUS0         0x002c
 +#define OMAP4_GPIO_IRQSTATUS1         0x0030
 +#define OMAP4_GPIO_IRQSTATUSSET0      0x0034
 +#define OMAP4_GPIO_IRQSTATUSSET1      0x0038
 +#define OMAP4_GPIO_IRQSTATUSCLR0      0x003c
 +#define OMAP4_GPIO_IRQSTATUSCLR1      0x0040
 +#define OMAP4_GPIO_IRQWAKEN0          0x0044
 +#define OMAP4_GPIO_IRQWAKEN1          0x0048
 +#define OMAP4_GPIO_SYSSTATUS          0x0104
 +#define OMAP4_GPIO_CTRL                       0x0130
 +#define OMAP4_GPIO_OE                 0x0134
 +#define OMAP4_GPIO_DATAIN             0x0138
 +#define OMAP4_GPIO_DATAOUT            0x013c
 +#define OMAP4_GPIO_LEVELDETECT0               0x0140
 +#define OMAP4_GPIO_LEVELDETECT1               0x0144
 +#define OMAP4_GPIO_RISINGDETECT               0x0148
 +#define OMAP4_GPIO_FALLINGDETECT      0x014c
 +#define OMAP4_GPIO_DEBOUNCENABLE      0x0150
 +#define OMAP4_GPIO_DEBOUNCINGTIME     0x0154
 +#define OMAP4_GPIO_CLEARDATAOUT               0x0190
 +#define OMAP4_GPIO_SETDATAOUT         0x0194
  /*
   * omap34xx specific GPIO registers
   */
  
- #define OMAP34XX_GPIO1_BASE           IO_ADDRESS(0x48310000)
- #define OMAP34XX_GPIO2_BASE           IO_ADDRESS(0x49050000)
- #define OMAP34XX_GPIO3_BASE           IO_ADDRESS(0x49052000)
- #define OMAP34XX_GPIO4_BASE           IO_ADDRESS(0x49054000)
- #define OMAP34XX_GPIO5_BASE           IO_ADDRESS(0x49056000)
- #define OMAP34XX_GPIO6_BASE           IO_ADDRESS(0x49058000)
+ #define OMAP34XX_GPIO1_BASE           OMAP2_IO_ADDRESS(0x48310000)
+ #define OMAP34XX_GPIO2_BASE           OMAP2_IO_ADDRESS(0x49050000)
+ #define OMAP34XX_GPIO3_BASE           OMAP2_IO_ADDRESS(0x49052000)
+ #define OMAP34XX_GPIO4_BASE           OMAP2_IO_ADDRESS(0x49054000)
+ #define OMAP34XX_GPIO5_BASE           OMAP2_IO_ADDRESS(0x49056000)
+ #define OMAP34XX_GPIO6_BASE           OMAP2_IO_ADDRESS(0x49058000)
  
  /*
   * OMAP44XX  specific GPIO registers
   */
- #define OMAP44XX_GPIO1_BASE             IO_ADDRESS(0x4a310000)
- #define OMAP44XX_GPIO2_BASE             IO_ADDRESS(0x48055000)
- #define OMAP44XX_GPIO3_BASE             IO_ADDRESS(0x48057000)
- #define OMAP44XX_GPIO4_BASE             IO_ADDRESS(0x48059000)
- #define OMAP44XX_GPIO5_BASE             IO_ADDRESS(0x4805B000)
- #define OMAP44XX_GPIO6_BASE             IO_ADDRESS(0x4805D000)
- 
- #define OMAP_MPUIO_VBASE              IO_ADDRESS(OMAP_MPUIO_BASE)
+ #define OMAP44XX_GPIO1_BASE             OMAP2_IO_ADDRESS(0x4a310000)
+ #define OMAP44XX_GPIO2_BASE             OMAP2_IO_ADDRESS(0x48055000)
+ #define OMAP44XX_GPIO3_BASE             OMAP2_IO_ADDRESS(0x48057000)
+ #define OMAP44XX_GPIO4_BASE             OMAP2_IO_ADDRESS(0x48059000)
+ #define OMAP44XX_GPIO5_BASE             OMAP2_IO_ADDRESS(0x4805B000)
+ #define OMAP44XX_GPIO6_BASE             OMAP2_IO_ADDRESS(0x4805D000)
  
  struct gpio_bank {
        void __iomem *base;
@@@ -221,7 -195,7 +221,7 @@@
  
  #ifdef CONFIG_ARCH_OMAP16XX
  static struct gpio_bank gpio_bank_1610[5] = {
-       { OMAP_MPUIO_VBASE,    INT_MPUIO,           IH_MPUIO_BASE,     METHOD_MPUIO},
+       { OMAP1_MPUIO_VBASE,    INT_MPUIO,          IH_MPUIO_BASE,     METHOD_MPUIO},
        { OMAP1610_GPIO1_BASE, INT_GPIO_BANK1,      IH_GPIO_BASE,      METHOD_GPIO_1610 },
        { OMAP1610_GPIO2_BASE, INT_1610_GPIO_BANK2, IH_GPIO_BASE + 16, METHOD_GPIO_1610 },
        { OMAP1610_GPIO3_BASE, INT_1610_GPIO_BANK3, IH_GPIO_BASE + 32, METHOD_GPIO_1610 },
@@@ -231,14 -205,14 +231,14 @@@
  
  #ifdef CONFIG_ARCH_OMAP15XX
  static struct gpio_bank gpio_bank_1510[2] = {
-       { OMAP_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
+       { OMAP1_MPUIO_VBASE,   INT_MPUIO,      IH_MPUIO_BASE, METHOD_MPUIO },
        { OMAP1510_GPIO_BASE, INT_GPIO_BANK1, IH_GPIO_BASE,  METHOD_GPIO_1510 }
  };
  #endif
  
  #ifdef CONFIG_ARCH_OMAP730
  static struct gpio_bank gpio_bank_730[7] = {
-       { OMAP_MPUIO_VBASE,    INT_730_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
+       { OMAP1_MPUIO_VBASE,    INT_730_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
        { OMAP730_GPIO1_BASE,  INT_730_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_730 },
        { OMAP730_GPIO2_BASE,  INT_730_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_730 },
        { OMAP730_GPIO3_BASE,  INT_730_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_730 },
@@@ -250,7 -224,7 +250,7 @@@
  
  #ifdef CONFIG_ARCH_OMAP850
  static struct gpio_bank gpio_bank_850[7] = {
-       { OMAP_MPUIO_BASE,     INT_850_MPUIO,       IH_MPUIO_BASE,      METHOD_MPUIO },
+       { OMAP1_MPUIO_BASE,     INT_850_MPUIO,      IH_MPUIO_BASE,      METHOD_MPUIO },
        { OMAP850_GPIO1_BASE,  INT_850_GPIO_BANK1,  IH_GPIO_BASE,       METHOD_GPIO_850 },
        { OMAP850_GPIO2_BASE,  INT_850_GPIO_BANK2,  IH_GPIO_BASE + 32,  METHOD_GPIO_850 },
        { OMAP850_GPIO3_BASE,  INT_850_GPIO_BANK3,  IH_GPIO_BASE + 64,  METHOD_GPIO_850 },
@@@ -412,16 -386,12 +412,16 @@@ static void _set_gpio_direction(struct 
                reg += OMAP850_GPIO_DIR_CONTROL;
                break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_OE;
                break;
  #endif
 +#if defined(CONFIG_ARCH_OMAP4)
 +      case METHOD_GPIO_24XX:
 +              reg += OMAP4_GPIO_OE;
 +              break;
 +#endif
        default:
                WARN_ON(1);
                return;
@@@ -489,7 -459,8 +489,7 @@@ static void _set_gpio_dataout(struct gp
                        l &= ~(1 << gpio);
                break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        case METHOD_GPIO_24XX:
                if (enable)
                        reg += OMAP24XX_GPIO_SETDATAOUT;
@@@ -498,15 -469,6 +498,15 @@@
                l = 1 << gpio;
                break;
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +      case METHOD_GPIO_24XX:
 +              if (enable)
 +                      reg += OMAP4_GPIO_SETDATAOUT;
 +              else
 +                      reg += OMAP4_GPIO_CLEARDATAOUT;
 +              l = 1 << gpio;
 +              break;
 +#endif
        default:
                WARN_ON(1);
                return;
@@@ -547,16 -509,12 +547,16 @@@ static int _get_gpio_datain(struct gpio
                reg += OMAP850_GPIO_DATA_INPUT;
                break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_DATAIN;
                break;
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +      case METHOD_GPIO_24XX:
 +              reg += OMAP4_GPIO_DATAIN;
 +              break;
 +#endif
        default:
                return -EINVAL;
        }
@@@ -631,11 -589,7 +631,11 @@@ void omap_set_gpio_debounce(int gpio, i
  
        bank = get_gpio_bank(gpio);
        reg = bank->base;
 +#ifdef CONFIG_ARCH_OMAP4
 +      reg += OMAP4_GPIO_DEBOUNCENABLE;
 +#else
        reg += OMAP24XX_GPIO_DEBOUNCE_EN;
 +#endif
  
        spin_lock_irqsave(&bank->lock, flags);
        val = __raw_readl(reg);
@@@ -672,11 -626,7 +672,11 @@@ void omap_set_gpio_debounce_time(int gp
        reg = bank->base;
  
        enc_time &= 0xff;
 +#ifdef CONFIG_ARCH_OMAP4
 +      reg += OMAP4_GPIO_DEBOUNCINGTIME;
 +#else
        reg += OMAP24XX_GPIO_DEBOUNCE_VAL;
 +#endif
        __raw_writel(enc_time, reg);
  }
  EXPORT_SYMBOL(omap_set_gpio_debounce_time);
@@@ -688,46 -638,23 +688,46 @@@ static inline void set_24xx_gpio_trigge
  {
        void __iomem *base = bank->base;
        u32 gpio_bit = 1 << gpio;
 +      u32 val;
  
 -      MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
 -              trigger & IRQ_TYPE_LEVEL_LOW);
 -      MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
 -              trigger & IRQ_TYPE_LEVEL_HIGH);
 -      MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
 -              trigger & IRQ_TYPE_EDGE_RISING);
 -      MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
 -              trigger & IRQ_TYPE_EDGE_FALLING);
 -
 +      if (cpu_is_omap44xx()) {
 +              MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT0, gpio_bit,
 +                      trigger & IRQ_TYPE_LEVEL_LOW);
 +              MOD_REG_BIT(OMAP4_GPIO_LEVELDETECT1, gpio_bit,
 +                      trigger & IRQ_TYPE_LEVEL_HIGH);
 +              MOD_REG_BIT(OMAP4_GPIO_RISINGDETECT, gpio_bit,
 +                      trigger & IRQ_TYPE_EDGE_RISING);
 +              MOD_REG_BIT(OMAP4_GPIO_FALLINGDETECT, gpio_bit,
 +                      trigger & IRQ_TYPE_EDGE_FALLING);
 +      } else {
 +              MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT0, gpio_bit,
 +                      trigger & IRQ_TYPE_LEVEL_LOW);
 +              MOD_REG_BIT(OMAP24XX_GPIO_LEVELDETECT1, gpio_bit,
 +                      trigger & IRQ_TYPE_LEVEL_HIGH);
 +              MOD_REG_BIT(OMAP24XX_GPIO_RISINGDETECT, gpio_bit,
 +                      trigger & IRQ_TYPE_EDGE_RISING);
 +              MOD_REG_BIT(OMAP24XX_GPIO_FALLINGDETECT, gpio_bit,
 +                      trigger & IRQ_TYPE_EDGE_FALLING);
 +      }
        if (likely(!(bank->non_wakeup_gpios & gpio_bit))) {
 -              if (trigger != 0)
 -                      __raw_writel(1 << gpio, bank->base
 +              if (cpu_is_omap44xx()) {
 +                      if (trigger != 0)
 +                              __raw_writel(1 << gpio, bank->base+
 +                                              OMAP4_GPIO_IRQWAKEN0);
 +                      else {
 +                              val = __raw_readl(bank->base +
 +                                                      OMAP4_GPIO_IRQWAKEN0);
 +                              __raw_writel(val & (~(1 << gpio)), bank->base +
 +                                                       OMAP4_GPIO_IRQWAKEN0);
 +                      }
 +              } else {
 +                      if (trigger != 0)
 +                              __raw_writel(1 << gpio, bank->base
                                        + OMAP24XX_GPIO_SETWKUENA);
 -              else
 -                      __raw_writel(1 << gpio, bank->base
 +                      else
 +                              __raw_writel(1 << gpio, bank->base
                                        + OMAP24XX_GPIO_CLEARWKUENA);
 +              }
        } else {
                if (trigger != 0)
                        bank->enabled_non_wakeup_gpios |= gpio_bit;
@@@ -735,15 -662,9 +735,15 @@@
                        bank->enabled_non_wakeup_gpios &= ~gpio_bit;
        }
  
 -      bank->level_mask =
 -              __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
 -              __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 +      if (cpu_is_omap44xx()) {
 +              bank->level_mask =
 +                      __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT0) |
 +                      __raw_readl(bank->base + OMAP4_GPIO_LEVELDETECT1);
 +      } else {
 +              bank->level_mask =
 +                      __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0) |
 +                      __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
 +      }
  }
  #endif
  
@@@ -907,16 -828,12 +907,16 @@@ static void _clear_gpio_irqbank(struct 
                reg += OMAP850_GPIO_INT_STATUS;
                break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                              defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_IRQSTATUS1;
                break;
  #endif
 +#if defined(CONFIG_ARCH_OMAP4)
 +      case METHOD_GPIO_24XX:
 +              reg += OMAP4_GPIO_IRQSTATUS0;
 +              break;
 +#endif
        default:
                WARN_ON(1);
                return;
@@@ -926,16 -843,12 +926,16 @@@
        /* Workaround for clearing DSP GPIO interrupts to allow retention */
  #if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        reg = bank->base + OMAP24XX_GPIO_IRQSTATUS2;
 -      if (cpu_is_omap24xx() || cpu_is_omap34xx())
 +#endif
 +#if defined(CONFIG_ARCH_OMAP4)
 +      reg = bank->base + OMAP4_GPIO_IRQSTATUS1;
 +#endif
 +      if (cpu_is_omap24xx() || cpu_is_omap34xx() || cpu_is_omap44xx()) {
                __raw_writel(gpio_mask, reg);
  
        /* Flush posted write for the irq status to avoid spurious interrupts */
        __raw_readl(reg);
 -#endif
 +      }
  }
  
  static inline void _clear_gpio_irqstatus(struct gpio_bank *bank, int gpio)
@@@ -985,18 -898,13 +985,18 @@@ static u32 _get_gpio_irqbank_mask(struc
                inv = 1;
                break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                              defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        case METHOD_GPIO_24XX:
                reg += OMAP24XX_GPIO_IRQENABLE1;
                mask = 0xffffffff;
                break;
  #endif
 +#if defined(CONFIG_ARCH_OMAP4)
 +      case METHOD_GPIO_24XX:
 +              reg += OMAP4_GPIO_IRQSTATUSSET0;
 +              mask = 0xffffffff;
 +              break;
 +#endif
        default:
                WARN_ON(1);
                return 0;
@@@ -1064,7 -972,8 +1064,7 @@@ static void _enable_gpio_irqbank(struc
                        l |= gpio_mask;
                break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -              defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        case METHOD_GPIO_24XX:
                if (enable)
                        reg += OMAP24XX_GPIO_SETIRQENABLE1;
@@@ -1073,15 -982,6 +1073,15 @@@
                l = gpio_mask;
                break;
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +      case METHOD_GPIO_24XX:
 +              if (enable)
 +                      reg += OMAP4_GPIO_IRQSTATUSSET0;
 +              else
 +                      reg += OMAP4_GPIO_IRQSTATUSCLR0;
 +              l = gpio_mask;
 +              break;
 +#endif
        default:
                WARN_ON(1);
                return;
@@@ -1257,14 -1157,11 +1257,14 @@@ static void gpio_irq_handler(unsigned i
        if (bank->method == METHOD_GPIO_850)
                isr_reg = bank->base + OMAP850_GPIO_INT_STATUS;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                              defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
        if (bank->method == METHOD_GPIO_24XX)
                isr_reg = bank->base + OMAP24XX_GPIO_IRQSTATUS1;
  #endif
 +#if defined(CONFIG_ARCH_OMAP4)
 +      if (bank->method == METHOD_GPIO_24XX)
 +              isr_reg = bank->base + OMAP4_GPIO_IRQSTATUS0;
 +#endif
        while(1) {
                u32 isr_saved, level_mask = 0;
                u32 enabled;
@@@ -1418,9 -1315,8 +1418,9 @@@ static struct irq_chip mpuio_irq_chip 
  
  #include <linux/platform_device.h>
  
 -static int omap_mpuio_suspend_late(struct platform_device *pdev, pm_message_t mesg)
 +static int omap_mpuio_suspend_noirq(struct device *dev)
  {
 +      struct platform_device *pdev = to_platform_device(dev);
        struct gpio_bank        *bank = platform_get_drvdata(pdev);
        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
        unsigned long           flags;
@@@ -1433,9 -1329,8 +1433,9 @@@
        return 0;
  }
  
 -static int omap_mpuio_resume_early(struct platform_device *pdev)
 +static int omap_mpuio_resume_noirq(struct device *dev)
  {
 +      struct platform_device *pdev = to_platform_device(dev);
        struct gpio_bank        *bank = platform_get_drvdata(pdev);
        void __iomem            *mask_reg = bank->base + OMAP_MPUIO_GPIO_MASKIT;
        unsigned long           flags;
@@@ -1447,18 -1342,14 +1447,18 @@@
        return 0;
  }
  
 +static struct dev_pm_ops omap_mpuio_dev_pm_ops = {
 +      .suspend_noirq = omap_mpuio_suspend_noirq,
 +      .resume_noirq = omap_mpuio_resume_noirq,
 +};
 +
  /* use platform_driver for this, now that there's no longer any
   * point to sys_device (other than not disturbing old code).
   */
  static struct platform_driver omap_mpuio_driver = {
 -      .suspend_late   = omap_mpuio_suspend_late,
 -      .resume_early   = omap_mpuio_resume_early,
        .driver         = {
                .name   = "mpuio",
 +              .pm     = &omap_mpuio_dev_pm_ops,
        },
  };
  
@@@ -1747,7 -1638,7 +1747,7 @@@ static int __init _omap_gpio_init(void
  
                gpio_bank_count = OMAP34XX_NR_GPIOS;
                gpio_bank = gpio_bank_44xx;
 -              rev = __raw_readl(gpio_bank[0].base + OMAP24XX_GPIO_REVISION);
 +              rev = __raw_readl(gpio_bank[0].base + OMAP4_GPIO_REVISION);
                printk(KERN_INFO "OMAP44xx GPIO hardware version %d.%d\n",
                        (rev >> 4) & 0x0f, rev & 0x0f);
        }
@@@ -1781,16 -1672,7 +1781,16 @@@
                        static const u32 non_wakeup_gpios[] = {
                                0xe203ffc0, 0x08700040
                        };
 -
 +              if (cpu_is_omap44xx()) {
 +                      __raw_writel(0xffffffff, bank->base +
 +                                              OMAP4_GPIO_IRQSTATUSCLR0);
 +                      __raw_writew(0x0015, bank->base +
 +                                              OMAP4_GPIO_SYSCONFIG);
 +                      __raw_writel(0x00000000, bank->base +
 +                                               OMAP4_GPIO_DEBOUNCENABLE);
 +                      /* Initialize interface clock ungated, module enabled */
 +                      __raw_writel(0, bank->base + OMAP4_GPIO_CTRL);
 +              } else {
                        __raw_writel(0x00000000, bank->base + OMAP24XX_GPIO_IRQENABLE1);
                        __raw_writel(0xffffffff, bank->base + OMAP24XX_GPIO_IRQSTATUS1);
                        __raw_writew(0x0015, bank->base + OMAP24XX_GPIO_SYSCONFIG);
@@@ -1798,12 -1680,12 +1798,12 @@@
  
                        /* Initialize interface clock ungated, module enabled */
                        __raw_writel(0, bank->base + OMAP24XX_GPIO_CTRL);
 +              }
                        if (i < ARRAY_SIZE(non_wakeup_gpios))
                                bank->non_wakeup_gpios = non_wakeup_gpios[i];
                        gpio_count = 32;
                }
  #endif
 -
                /* REVISIT eventually switch from OMAP-specific gpio structs
                 * over to the generic ones
                 */
@@@ -1889,20 -1771,14 +1889,20 @@@ static int omap_gpio_suspend(struct sys
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                        break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                              defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                case METHOD_GPIO_24XX:
                        wake_status = bank->base + OMAP24XX_GPIO_WAKE_EN;
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                        break;
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +              case METHOD_GPIO_24XX:
 +                      wake_status = bank->base + OMAP4_GPIO_IRQWAKEN0;
 +                      wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
 +                      wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
 +                      break;
 +#endif
                default:
                        continue;
                }
@@@ -1937,18 -1813,13 +1937,18 @@@ static int omap_gpio_resume(struct sys_
                        wake_set = bank->base + OMAP1610_GPIO_SET_WAKEUPENA;
                        break;
  #endif
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                case METHOD_GPIO_24XX:
                        wake_clear = bank->base + OMAP24XX_GPIO_CLEARWKUENA;
                        wake_set = bank->base + OMAP24XX_GPIO_SETWKUENA;
                        break;
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +              case METHOD_GPIO_24XX:
 +                      wake_clear = bank->base + OMAP4_GPIO_IRQWAKEN0;
 +                      wake_set = bank->base + OMAP4_GPIO_IRQWAKEN0;
 +                      break;
 +#endif
                default:
                        continue;
                }
@@@ -1992,29 -1863,21 +1992,29 @@@ void omap2_gpio_prepare_for_retention(v
  
                if (!(bank->enabled_non_wakeup_gpios))
                        continue;
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                              defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                bank->saved_datain = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
                l1 = __raw_readl(bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                l2 = __raw_readl(bank->base + OMAP24XX_GPIO_RISINGDETECT);
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +              bank->saved_datain = __raw_readl(bank->base +
 +                                                      OMAP4_GPIO_DATAIN);
 +              l1 = __raw_readl(bank->base + OMAP4_GPIO_FALLINGDETECT);
 +              l2 = __raw_readl(bank->base + OMAP4_GPIO_RISINGDETECT);
 +#endif
                bank->saved_fallingdetect = l1;
                bank->saved_risingdetect = l2;
                l1 &= ~bank->enabled_non_wakeup_gpios;
                l2 &= ~bank->enabled_non_wakeup_gpios;
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                __raw_writel(l1, bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                __raw_writel(l2, bank->base + OMAP24XX_GPIO_RISINGDETECT);
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +              __raw_writel(l1, bank->base + OMAP4_GPIO_FALLINGDETECT);
 +              __raw_writel(l2, bank->base + OMAP4_GPIO_RISINGDETECT);
 +#endif
                c++;
        }
        if (!c) {
@@@ -2032,54 -1895,57 +2032,73 @@@ void omap2_gpio_resume_after_retention(
                return;
        for (i = 0; i < gpio_bank_count; i++) {
                struct gpio_bank *bank = &gpio_bank[i];
-               u32 l;
+               u32 l, gen, gen0, gen1;
  
                if (!(bank->enabled_non_wakeup_gpios))
                        continue;
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                __raw_writel(bank->saved_fallingdetect,
                                 bank->base + OMAP24XX_GPIO_FALLINGDETECT);
                __raw_writel(bank->saved_risingdetect,
                                 bank->base + OMAP24XX_GPIO_RISINGDETECT);
 +              l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
 +#endif
 +#ifdef CONFIG_ARCH_OMAP4
 +              __raw_writel(bank->saved_fallingdetect,
 +                               bank->base + OMAP4_GPIO_FALLINGDETECT);
 +              __raw_writel(bank->saved_risingdetect,
 +                               bank->base + OMAP4_GPIO_RISINGDETECT);
 +              l = __raw_readl(bank->base + OMAP4_GPIO_DATAIN);
  #endif
                /* Check if any of the non-wakeup interrupt GPIOs have changed
                 * state.  If so, generate an IRQ by software.  This is
                 * horribly racy, but it's the best we can do to work around
                 * this silicon bug. */
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 -              l = __raw_readl(bank->base + OMAP24XX_GPIO_DATAIN);
 -#endif
                l ^= bank->saved_datain;
                l &= bank->non_wakeup_gpios;
-               if (l) {
+ 
+               /*
+                * No need to generate IRQs for the rising edge for gpio IRQs
+                * configured with falling edge only; and vice versa.
+                */
+               gen0 = l & bank->saved_fallingdetect;
+               gen0 &= bank->saved_datain;
+ 
+               gen1 = l & bank->saved_risingdetect;
+               gen1 &= ~(bank->saved_datain);
+ 
+               /* FIXME: Consider GPIO IRQs with level detections properly! */
+               gen = l & (~(bank->saved_fallingdetect) &
+                               ~(bank->saved_risingdetect));
+               /* Consider all GPIO IRQs needed to be updated */
+               gen |= gen0 | gen1;
+ 
+               if (gen) {
                        u32 old0, old1;
 -#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX) || \
 -                      defined(CONFIG_ARCH_OMAP4)
 +#if defined(CONFIG_ARCH_OMAP24XX) || defined(CONFIG_ARCH_OMAP34XX)
                        old0 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                        old1 = __raw_readl(bank->base + OMAP24XX_GPIO_LEVELDETECT1);
-                       __raw_writel(old0 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
-                       __raw_writel(old1 | l, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
+                       __raw_writel(old0 | gen, bank->base +
+                                       OMAP24XX_GPIO_LEVELDETECT0);
+                       __raw_writel(old1 | gen, bank->base +
+                                       OMAP24XX_GPIO_LEVELDETECT1);
                        __raw_writel(old0, bank->base + OMAP24XX_GPIO_LEVELDETECT0);
                        __raw_writel(old1, bank->base + OMAP24XX_GPIO_LEVELDETECT1);
  #endif
 +#ifdef CONFIG_ARCH_OMAP4
 +                      old0 = __raw_readl(bank->base +
 +                                              OMAP4_GPIO_LEVELDETECT0);
 +                      old1 = __raw_readl(bank->base +
 +                                              OMAP4_GPIO_LEVELDETECT1);
 +                      __raw_writel(old0 | l, bank->base +
 +                                              OMAP4_GPIO_LEVELDETECT0);
 +                      __raw_writel(old1 | l, bank->base +
 +                                              OMAP4_GPIO_LEVELDETECT1);
 +                      __raw_writel(old0, bank->base +
 +                                              OMAP4_GPIO_LEVELDETECT0);
 +                      __raw_writel(old1, bank->base +
 +                                              OMAP4_GPIO_LEVELDETECT1);
 +#endif
                }
        }