fix PCI and AGP posting problems (based on testing by Chris Ison and

    suggestions by Benjamin Herrenschmidt and Arjan van de Ven)
remove radeon_flush_write_combine() which has been unused for a while

diff --git a/shared-core/radeon_drv.h b/shared-core/radeon_drv.h
index 22c5d04..fb8fbaf 100644 (file)
--- a/shared-core/radeon_drv.h
+++ b/shared-core/radeon_drv.h
@@ -824,13 +824,6 @@ do {                                                                       \
  * Ring control
  */
 
-#if defined(__powerpc__)
-#define radeon_flush_write_combine()   (void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define radeon_flush_write_combine()   DRM_WRITEMEMORYBARRIER()
-#endif
-
-
 #define RADEON_VERBOSE 0
 
 #define RING_LOCALS    int write, _nr; unsigned int mask; u32 *ring;
@@ -864,8 +857,13 @@ do {                                                                       \
                dev_priv->ring.tail = write;                            \
 } while (0)
 
-#define COMMIT_RING() do {                                         \
-       RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );             \
+#define COMMIT_RING() do {                                             \
+       /* Flush writes to ring */                                      \
+       DRM_READMEMORYBARRIER();                                        \
+       GET_RING_HEAD( &dev_priv->ring );                               \
+       RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );         \
+       /* read from PCI bus to ensure correct posting */               \
+       RADEON_READ( RADEON_CP_RB_RPTR );                               \
 } while (0)
 
 #define OUT_RING( x ) do {                                             \

diff --git a/shared/radeon_drv.h b/shared/radeon_drv.h
index 22c5d04..fb8fbaf 100644 (file)
--- a/shared/radeon_drv.h
+++ b/shared/radeon_drv.h
@@ -824,13 +824,6 @@ do {                                                                       \
  * Ring control
  */
 
-#if defined(__powerpc__)
-#define radeon_flush_write_combine()   (void) GET_RING_HEAD( &dev_priv->ring )
-#else
-#define radeon_flush_write_combine()   DRM_WRITEMEMORYBARRIER()
-#endif
-
-
 #define RADEON_VERBOSE 0
 
 #define RING_LOCALS    int write, _nr; unsigned int mask; u32 *ring;
@@ -864,8 +857,13 @@ do {                                                                       \
                dev_priv->ring.tail = write;                            \
 } while (0)
 
-#define COMMIT_RING() do {                                         \
-       RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );             \
+#define COMMIT_RING() do {                                             \
+       /* Flush writes to ring */                                      \
+       DRM_READMEMORYBARRIER();                                        \
+       GET_RING_HEAD( &dev_priv->ring );                               \
+       RADEON_WRITE( RADEON_CP_RB_WPTR, dev_priv->ring.tail );         \
+       /* read from PCI bus to ensure correct posting */               \
+       RADEON_READ( RADEON_CP_RB_RPTR );                               \
 } while (0)
 
 #define OUT_RING( x ) do {                                             \