ARM: sun5i: Allow PLL3 2x fixed factor clock to change PLL3 rate

In order to be able to properly generate its pixel clock, the pll3-2x fixed
factor needs to be able to change the PLL3 rate too.

Add the needed extra compatible so that it behaves that way.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>

diff --git a/arch/arm/boot/dts/sun5i.dtsi b/arch/arm/boot/dts/sun5i.dtsi
index 0840612b5ed6ddcc875c539f5416b6bdc8558e76..e374f4fc8073f6fde9ee0d5d0d5d4758218a264d 100644 (file)
--- a/arch/arm/boot/dts/sun5i.dtsi
+++ b/arch/arm/boot/dts/sun5i.dtsi
@@ -130,7 +130,7 @@
                };
 
                pll3x2: pll3x2_clk {
-                       compatible = "fixed-factor-clock";
+                       compatible = "allwinner,sun4i-a10-pll3-2x-clk", "fixed-factor-clock";
                        #clock-cells = <0>;
                        clock-div = <1>;
                        clock-mult = <2>;