PCI: iproc: Add CRS check in config read

The IPROC PCIe host controller implementation returns CFG_RETRY_STATUS
(0xffff0001) data when it receives a CRS completion, regardless of the
address of the read or the CRS Software Visibility Enable bit. As a
workaround the driver retries in software any read that returns
CFG_RETRY_STATUS even though, for reads of registers that are not Vendor
ID, the register value can correspond to CFG_RETRY_STATUS; this
situation would cause a timeout and failure of reading a valid register
value.

IPROC PCIe host controller PAXB v2 has a register to show config read
status flags like SC, UR, CRS and CA. Using this status flag,
an extra check is added to confirm the CRS using status flags before
reissuing a config read, fixing the issue.

Signed-off-by: Srinath Mannam <srinath.mannam@broadcom.com>
[lorenzo.pieralisi@arm.com: rewrote commit log]
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: Scott Branden <scott.branden@broadcom.com>

diff --git a/drivers/pci/controller/pcie-iproc.c b/drivers/pci/controller/pcie-iproc.c
index c20fd6b..b882255 100644 (file)
--- a/drivers/pci/controller/pcie-iproc.c
+++ b/drivers/pci/controller/pcie-iproc.c
@@ -60,6 +60,10 @@
 #define APB_ERR_EN_SHIFT               0
 #define APB_ERR_EN                     BIT(APB_ERR_EN_SHIFT)
 
+#define CFG_RD_SUCCESS                 0
+#define CFG_RD_UR                      1
+#define CFG_RD_CRS                     2
+#define CFG_RD_CA                      3
 #define CFG_RETRY_STATUS               0xffff0001
 #define CFG_RETRY_STATUS_TIMEOUT_US    500000 /* 500 milliseconds */
 
@@ -289,6 +293,9 @@ enum iproc_pcie_reg {
        IPROC_PCIE_IARR4,
        IPROC_PCIE_IMAP4,
 
+       /* config read status */
+       IPROC_PCIE_CFG_RD_STATUS,
+
        /* link status */
        IPROC_PCIE_LINK_STATUS,
 
@@ -350,6 +357,7 @@ static const u16 iproc_pcie_reg_paxb_v2[] = {
        [IPROC_PCIE_IMAP3]              = 0xe08,
        [IPROC_PCIE_IARR4]              = 0xe68,
        [IPROC_PCIE_IMAP4]              = 0xe70,
+       [IPROC_PCIE_CFG_RD_STATUS]      = 0xee0,
        [IPROC_PCIE_LINK_STATUS]        = 0xf0c,
        [IPROC_PCIE_APB_ERR_EN]         = 0xf40,
 };
@@ -474,10 +482,12 @@ static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
        return (pcie->base + offset);
 }
 
-static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
+static unsigned int iproc_pcie_cfg_retry(struct iproc_pcie *pcie,
+                                        void __iomem *cfg_data_p)
 {
        int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
        unsigned int data;
+       u32 status;
 
        /*
         * As per PCIe spec r3.1, sec 2.3.2, CRS Software Visibility only
@@ -498,6 +508,15 @@ static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
         */
        data = readl(cfg_data_p);
        while (data == CFG_RETRY_STATUS && timeout--) {
+               /*
+                * CRS state is set in CFG_RD status register
+                * This will handle the case where CFG_RETRY_STATUS is
+                * valid config data.
+                */
+               status = iproc_pcie_read_reg(pcie, IPROC_PCIE_CFG_RD_STATUS);
+               if (status != CFG_RD_CRS)
+                       return data;
+
                udelay(1);
                data = readl(cfg_data_p);
        }
@@ -576,7 +595,7 @@ static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
        if (!cfg_data_p)
                return PCIBIOS_DEVICE_NOT_FOUND;
 
-       data = iproc_pcie_cfg_retry(cfg_data_p);
+       data = iproc_pcie_cfg_retry(pcie, cfg_data_p);
 
        *val = data;
        if (size <= 2)