compatible = "starfive,jh7110-dma", "snps,axi-dma-1.01a";
reg = <0x0 0x16050000 0x0 0x10000>;
clocks = <&clkgen JH7110_DMA1P_CLK_AXI>,
- <&clkgen JH7110_DMA1P_CLK_AHB>;
- clock-names = "core-clk", "cfgr-clk";
+ <&clkgen JH7110_DMA1P_CLK_AHB>,
+ <&clkgen JH7110_NOC_BUS_CLK_STG_AXI>;
+ clock-names = "core-clk", "cfgr-clk", "stg_clk";
resets = <&rstgen RSTN_U0_DW_DMA1P_AXI>,
- <&rstgen RSTN_U0_DW_DMA1P_AHB>;
- reset-names = "rst_axi", "rst_ahb";
+ <&rstgen RSTN_U0_DW_DMA1P_AHB>,
+ <&rstgen RSTN_U0_NOC_BUS_STG_AXI_N>;
+ reset-names = "rst_axi", "rst_ahb", "rst_stg";
interrupts = <73>;
#dma-cells = <2>;
dma-channels = <4>;
clk_disable_unprepare(chip->core_clk);
clk_disable_unprepare(chip->cfgr_clk);
+ clk_disable_unprepare(chip->axi_clk);
return 0;
}
{
int ret;
+ ret = clk_prepare_enable(chip->axi_clk);
+ if (ret < 0)
+ return ret;
+
ret = clk_prepare_enable(chip->cfgr_clk);
if (ret < 0)
return ret;
return PTR_ERR(chip->apb_regs);
}
+ chip->axi_clk = devm_clk_get(chip->dev, "stg_clk");
+ if (IS_ERR(chip->axi_clk))
+ return PTR_ERR(chip->axi_clk);
+
chip->core_clk = devm_clk_get(chip->dev, "core-clk");
if (IS_ERR(chip->core_clk))
return PTR_ERR(chip->core_clk);
if (IS_ERR(chip->cfgr_clk))
return PTR_ERR(chip->cfgr_clk);
+ chip->rst_axi = devm_reset_control_get_exclusive(&pdev->dev, "rst_stg");
+ if (IS_ERR(chip->rst_axi)) {
+ dev_err(&pdev->dev, "%s: failed to get rst_stg reset control\n", __func__);
+ return PTR_ERR(chip->rst_axi);
+ }
chip->rst_core = devm_reset_control_get_exclusive(&pdev->dev, "rst_axi");
if (IS_ERR(chip->rst_core)) {
dev_err(&pdev->dev, "%s: failed to get rst_core reset control\n", __func__);
return PTR_ERR(chip->rst_cfgr);
}
+ reset_control_deassert(chip->rst_axi);
reset_control_deassert(chip->rst_core);
reset_control_deassert(chip->rst_cfgr);
u32 i;
/* Enable clk before accessing to registers */
+ clk_prepare_enable(chip->axi_clk);
clk_prepare_enable(chip->cfgr_clk);
clk_prepare_enable(chip->core_clk);
axi_dma_irq_disable(chip);