default SHMOBILE_TIMER_HZ if ARCH_SHMOBILE
default 100
+config SCHED_HRTICK
+ def_bool HIGH_RES_TIMERS
+
config THUMB2_KERNEL
- bool "Compile the kernel in Thumb-2 mode"
+ bool "Compile the kernel in Thumb-2 mode" if !CPU_THUMBONLY
depends on CPU_V7 && !CPU_V6 && !CPU_V6K
+ default y if CPU_THUMBONLY
select AEABI
select ARM_ASM_UNIFIED
select ARM_UNWIND
#define MPIDR_AFFINITY_LEVEL(mpidr, level) \
((mpidr >> (MPIDR_LEVEL_BITS * level)) & MPIDR_LEVEL_MASK)
++#define ARM_CPU_IMP_ARM 0x41
++#define ARM_CPU_IMP_INTEL 0x69
++
++#define ARM_CPU_PART_ARM1136 0xB360
++#define ARM_CPU_PART_ARM1156 0xB560
++#define ARM_CPU_PART_ARM1176 0xB760
++#define ARM_CPU_PART_ARM11MPCORE 0xB020
++#define ARM_CPU_PART_CORTEX_A8 0xC080
++#define ARM_CPU_PART_CORTEX_A9 0xC090
++#define ARM_CPU_PART_CORTEX_A5 0xC050
++#define ARM_CPU_PART_CORTEX_A15 0xC0F0
++#define ARM_CPU_PART_CORTEX_A7 0xC070
++
++#define ARM_CPU_XSCALE_ARCH_MASK 0xe000
++#define ARM_CPU_XSCALE_ARCH_V1 0x2000
++#define ARM_CPU_XSCALE_ARCH_V2 0x4000
++#define ARM_CPU_XSCALE_ARCH_V3 0x6000
++
extern unsigned int processor_id;
#ifdef CONFIG_CPU_CP15
return read_cpuid(CPUID_ID);
}
+ #else /* ifdef CONFIG_CPU_CP15 */
+
+ static inline unsigned int __attribute_const__ read_cpuid_id(void)
+ {
+ return processor_id;
+ }
+
+ #endif /* ifdef CONFIG_CPU_CP15 / else */
+
+static inline unsigned int __attribute_const__ read_cpuid_implementor(void)
+{
+ return (read_cpuid_id() & 0xFF000000) >> 24;
+}
+
+static inline unsigned int __attribute_const__ read_cpuid_part_number(void)
+{
+ return read_cpuid_id() & 0xFFF0;
+}
+
+static inline unsigned int __attribute_const__ xscale_cpu_arch_version(void)
+{
+ return read_cpuid_part_number() & ARM_CPU_XSCALE_ARCH_MASK;
+}
+
static inline unsigned int __attribute_const__ read_cpuid_cachetype(void)
{
return read_cpuid(CPUID_CACHETYPE);