#define LLVM_CODEGEN_TARGETREGISTERINFO_H
#include "llvm/ADT/ArrayRef.h"
+#include "llvm/ADT/Optional.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/StringRef.h"
#include "llvm/ADT/iterator_range.h"
/// markSuperRegs() and checkAllSuperRegsMarked() in this case.
virtual BitVector getReservedRegs(const MachineFunction &MF) const = 0;
+ /// Returns either a string explaining why the given register is reserved for
+ /// this function, or an empty optional if no explanation has been written.
+ /// The absence of an explanation does not mean that the register is not
+ /// reserved (meaning, you should check that PhysReg is in fact reserved
+ /// before calling this).
+ virtual llvm::Optional<std::string>
+ explainReservedReg(const MachineFunction &MF, MCRegister PhysReg) const {
+ return {};
+ }
+
/// Returns false if we can't guarantee that Physreg, specified as an IR asm
/// clobber constraint, will be preserved across the statement.
virtual bool isAsmClobberable(const MachineFunction &MF,
LocCookie, Msg, DiagnosticSeverity::DS_Warning));
MMI->getModule()->getContext().diagnose(
DiagnosticInfoInlineAsm(LocCookie, Note, DiagnosticSeverity::DS_Note));
+
+ for (const Register RR : RestrRegs) {
+ if (llvm::Optional<std::string> reason =
+ TRI->explainReservedReg(*MF, RR)) {
+ MMI->getModule()->getContext().diagnose(DiagnosticInfoInlineAsm(
+ LocCookie, *reason, DiagnosticSeverity::DS_Note));
+ }
+ }
}
emitInlineAsm(OS.str(), getSubtargetInfo(), TM.Options.MCOptions, LocMD,
return CSR_AArch64_StackProbe_Windows_RegMask;
}
+llvm::Optional<std::string>
+AArch64RegisterInfo::explainReservedReg(const MachineFunction &MF,
+ MCRegister PhysReg) const {
+ if (hasBasePointer(MF) &&
+ (PhysReg == AArch64::X19 || PhysReg == AArch64::W19))
+ return std::string("X19 is used as the frame base pointer register.");
+
+ return {};
+}
+
BitVector
AArch64RegisterInfo::getStrictlyReservedRegs(const MachineFunction &MF) const {
const AArch64FrameLowering *TFI = getFrameLowering(MF);
BitVector getStrictlyReservedRegs(const MachineFunction &MF) const;
BitVector getReservedRegs(const MachineFunction &MF) const override;
+ llvm::Optional<std::string>
+ explainReservedReg(const MachineFunction &MF,
+ MCRegister PhysReg) const override;
bool isAsmClobberable(const MachineFunction &MF,
MCRegister PhysReg) const override;
const TargetRegisterClass *
--- /dev/null
+; Check that not only do we warn about clobbering x19 we also say
+; what it is used for.
+
+; RUN: llc <%s -mtriple=aarch64-none-eabi 2>&1 | FileCheck %s
+
+; CHECK: warning: inline asm clobber list contains reserved registers: X19
+; CHECK: note: X19 is used as the frame base pointer register.
+
+define void @alloca(i64 %size) {
+entry:
+ %a = alloca i128, i64 %size, align 64
+ call void asm sideeffect "nop", "~{x19}"()
+ ret void
+}
+