(vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
(vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
(do_maxnm): New function.
(insns): Add vmaxnm, vminnm entries.
* gas/testsuite/gas/testsuite/gas/armv8-a+fp.d: Update testcase.
* gas/testsuite/gas/testsuite/gas/armv8-a+fp.s: Likewise.
* gas/testsuite/gas/testsuite/gas/armv8-a+simd.d: New testcase.
* gas/testsuite/gas/testsuite/gas/armv8-a+simd.s: Likewise.
* opcodes/arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
(neon_opcodes): Likewise.
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * config/tc-arm.c (NEON_ENC_TAB): Add vmaxnm, vminnm entries.
+ (vfp_or_neon_is_neon_bits): Add NEON_CHECK_ARCH8 enumerator.
+ (vfp_or_neon_is_neon): Add check for SIMD for ARMv8.
+ (do_maxnm): New function.
+ (insns): Add vmaxnm, vminnm entries.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* config/tc-arm.c (NEON_ENC_TAB): Add entries for VSEL.
(NEON_ENC_FPV8_): New define.
(do_vfp_nsyn_fpv8): New function.
X(vseleq, 0xe000a00, N_INV, N_INV), \
X(vselvs, 0xe100a00, N_INV, N_INV), \
X(vselge, 0xe200a00, N_INV, N_INV), \
- X(vselgt, 0xe300a00, N_INV, N_INV)
+ X(vselgt, 0xe300a00, N_INV, N_INV), \
+ X(vmaxnm, 0xe800a00, 0x3000f10, N_INV), \
+ X(vminnm, 0xe800a40, 0x3200f10, N_INV)
enum neon_opc
{
enum vfp_or_neon_is_neon_bits
{
NEON_CHECK_CC = 1,
- NEON_CHECK_ARCH = 2
+ NEON_CHECK_ARCH = 2,
+ NEON_CHECK_ARCH8 = 4
};
/* Call this function if an instruction which may have belonged to the VFP or
}
if ((check & NEON_CHECK_ARCH)
- && !ARM_CPU_HAS_FEATURE (cpu_variant, fpu_neon_ext_v1))
+ && !mark_feature_used (&fpu_neon_ext_v1))
+ {
+ first_error (_(BAD_FPU));
+ return FAIL;
+ }
+
+ if ((check & NEON_CHECK_ARCH8)
+ && !mark_feature_used (&fpu_neon_ext_armv8))
{
first_error (_(BAD_FPU));
return FAIL;
first_error (_("invalid instruction shape"));
}
+static void
+do_vmaxnm (void)
+{
+ set_it_insn_type (OUTSIDE_IT_INSN);
+
+ if (try_vfp_nsyn (3, do_vfp_nsyn_fpv8) == SUCCESS)
+ return;
+
+ if (vfp_or_neon_is_neon (NEON_CHECK_CC | NEON_CHECK_ARCH8) == FAIL)
+ return;
+
+ neon_dyadic_misc (NT_untyped, N_F32, 0);
+}
+
\f
/* Overall per-instruction processing. */
nUF(vselvs, _vselvs, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vselge, _vselge, 3, (RVSD, RVSD, RVSD), vsel),
nUF(vselgt, _vselgt, 3, (RVSD, RVSD, RVSD), vsel),
+ nUF(vmaxnm, _vmaxnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
+ nUF(vminnm, _vminnm, 3, (RNSDQ, oRNSDQ, RNSDQ), vmaxnm),
#undef ARM_VARIANT
#define ARM_VARIANT & fpu_fpa_ext_v1 /* Core FPA instruction set (V1). */
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * gas/testsuite/gas/armv8-a+fp.d: Update testcase.
+ * gas/testsuite/gas/armv8-a+fp.s: Likewise.
+ * gas/testsuite/gas/armv8-a+simd.d: New testcase.
+ * gas/testsuite/gas/armv8-a+simd.s: Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* gas/arm/armv8-a+fp.d: New testcase.
* gas/arm/armv8-a+fp.s: Likewise.
0[0-9a-f]+ <[^>]+> fe500ba0 vselvs.f64 d16, d16, d16
0[0-9a-f]+ <[^>]+> fe2ffb0f vselge.f64 d15, d15, d15
0[0-9a-f]+ <[^>]+> fe7ffbaf vselgt.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a00 vmaxnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00aa0 vmaxnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa0f vmaxnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaaf vmaxnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b00 vmaxnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00ba0 vmaxnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb0f vmaxnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbaf vmaxnm.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe800a40 vminnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec00ae0 vminnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8ffa4f vminnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecffaef vminnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe800b40 vminnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec00be0 vminnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8ffb4f vminnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecffbef vminnm.f64 d31, d31, d31
0[0-9a-f]+ <[^>]+> fe00 0a00 vseleq.f32 s0, s0, s0
0[0-9a-f]+ <[^>]+> fe50 0aa0 vselvs.f32 s1, s1, s1
0[0-9a-f]+ <[^>]+> fe2f fa0f vselge.f32 s30, s30, s30
0[0-9a-f]+ <[^>]+> fe50 0ba0 vselvs.f64 d16, d16, d16
0[0-9a-f]+ <[^>]+> fe2f fb0f vselge.f64 d15, d15, d15
0[0-9a-f]+ <[^>]+> fe7f fbaf vselgt.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a00 vmaxnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0aa0 vmaxnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa0f vmaxnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faaf vmaxnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b00 vmaxnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0ba0 vmaxnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb0f vmaxnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbaf vmaxnm.f64 d31, d31, d31
+0[0-9a-f]+ <[^>]+> fe80 0a40 vminnm.f32 s0, s0, s0
+0[0-9a-f]+ <[^>]+> fec0 0ae0 vminnm.f32 s1, s1, s1
+0[0-9a-f]+ <[^>]+> fe8f fa4f vminnm.f32 s30, s30, s30
+0[0-9a-f]+ <[^>]+> fecf faef vminnm.f32 s31, s31, s31
+0[0-9a-f]+ <[^>]+> fe80 0b40 vminnm.f64 d0, d0, d0
+0[0-9a-f]+ <[^>]+> fec0 0be0 vminnm.f64 d16, d16, d16
+0[0-9a-f]+ <[^>]+> fe8f fb4f vminnm.f64 d15, d15, d15
+0[0-9a-f]+ <[^>]+> fecf fbef vminnm.f64 d31, d31, d31
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
+ vmaxnm.f32 s0, s0, s0
+ vmaxnm.f32 s1, s1, s1
+ vmaxnm.f32 s30, s30, s30
+ vmaxnm.f32 s31, s31, s31
+ vmaxnm.f64 d0, d0, d0
+ vmaxnm.f64 d16, d16, d16
+ vmaxnm.f64 d15, d15, d15
+ vmaxnm.f64 d31, d31, d31
+ vminnm.f32 s0, s0, s0
+ vminnm.f32 s1, s1, s1
+ vminnm.f32 s30, s30, s30
+ vminnm.f32 s31, s31, s31
+ vminnm.f64 d0, d0, d0
+ vminnm.f64 d16, d16, d16
+ vminnm.f64 d15, d15, d15
+ vminnm.f64 d31, d31, d31
.thumb
vseleq.f32 s0, s0, s0
vselvs.f64 d16, d16, d16
vselge.f64 d15, d15, d15
vselgt.f64 d31, d31, d31
+ vmaxnm.f32 s0, s0, s0
+ vmaxnm.f32 s1, s1, s1
+ vmaxnm.f32 s30, s30, s30
+ vmaxnm.f32 s31, s31, s31
+ vmaxnm.f64 d0, d0, d0
+ vmaxnm.f64 d16, d16, d16
+ vmaxnm.f64 d15, d15, d15
+ vmaxnm.f64 d31, d31, d31
+ vminnm.f32 s0, s0, s0
+ vminnm.f32 s1, s1, s1
+ vminnm.f32 s30, s30, s30
+ vminnm.f32 s31, s31, s31
+ vminnm.f64 d0, d0, d0
+ vminnm.f64 d16, d16, d16
+ vminnm.f64 d15, d15, d15
+ vminnm.f64 d31, d31, d31
--- /dev/null
+#name: Valid v8-a+simdv3
+#objdump: -dr --prefix-addresses --show-raw-insn
+
+.*: +file format .*arm.*
+
+Disassembly of section .text:
+0[0-9a-f]+ <[^>]+> f3000f10 vmaxnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3400fb0 vmaxnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> f30fff1f vmaxnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> f34fffbf vmaxnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3000f50 vmaxnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3400ff0 vmaxnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f30eef5e vmaxnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f34eeffe vmaxnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> f3200f10 vminnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> f3600fb0 vminnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> f32fff1f vminnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> f36fffbf vminnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> f3200f50 vminnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> f3600ff0 vminnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> f32eef5e vminnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> f36eeffe vminnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff00 0f10 vmaxnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff40 0fb0 vmaxnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff0f ff1f vmaxnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff4f ffbf vmaxnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff00 0f50 vmaxnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff40 0ff0 vmaxnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff0e ef5e vmaxnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff4e effe vmaxnm.f32 q15, q15, q15
+0[0-9a-f]+ <[^>]+> ff20 0f10 vminnm.f32 d0, d0, d0
+0[0-9a-f]+ <[^>]+> ff60 0fb0 vminnm.f32 d16, d16, d16
+0[0-9a-f]+ <[^>]+> ff2f ff1f vminnm.f32 d15, d15, d15
+0[0-9a-f]+ <[^>]+> ff6f ffbf vminnm.f32 d31, d31, d31
+0[0-9a-f]+ <[^>]+> ff20 0f50 vminnm.f32 q0, q0, q0
+0[0-9a-f]+ <[^>]+> ff60 0ff0 vminnm.f32 q8, q8, q8
+0[0-9a-f]+ <[^>]+> ff2e ef5e vminnm.f32 q7, q7, q7
+0[0-9a-f]+ <[^>]+> ff6e effe vminnm.f32 q15, q15, q15
--- /dev/null
+ .syntax unified
+ .arch armv8-a
+ .arch_extension simd
+
+ .arm
+ vmaxnm.f32 d0, d0, d0
+ vmaxnm.f32 d16, d16, d16
+ vmaxnm.f32 d15, d15, d15
+ vmaxnm.f32 d31, d31, d31
+ vmaxnm.f32 q0, q0, q0
+ vmaxnm.f32 q8, q8, q8
+ vmaxnm.f32 q7, q7, q7
+ vmaxnm.f32 q15, q15, q15
+ vminnm.f32 d0, d0, d0
+ vminnm.f32 d16, d16, d16
+ vminnm.f32 d15, d15, d15
+ vminnm.f32 d31, d31, d31
+ vminnm.f32 q0, q0, q0
+ vminnm.f32 q8, q8, q8
+ vminnm.f32 q7, q7, q7
+ vminnm.f32 q15, q15, q15
+
+ .thumb
+ vmaxnm.f32 d0, d0, d0
+ vmaxnm.f32 d16, d16, d16
+ vmaxnm.f32 d15, d15, d15
+ vmaxnm.f32 d31, d31, d31
+ vmaxnm.f32 q0, q0, q0
+ vmaxnm.f32 q8, q8, q8
+ vmaxnm.f32 q7, q7, q7
+ vmaxnm.f32 q15, q15, q15
+ vminnm.f32 d0, d0, d0
+ vminnm.f32 d16, d16, d16
+ vminnm.f32 d15, d15, d15
+ vminnm.f32 d31, d31, d31
+ vminnm.f32 q0, q0, q0
+ vminnm.f32 q8, q8, q8
+ vminnm.f32 q7, q7, q7
+ vminnm.f32 q15, q15, q15
2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+ * arm-dis.c (coprocessor_opcodes): Add VMAXNM/VMINNM.
+ (neon_opcodes): Likewise.
+
+2012-08-24 Matthew Gretton-Dann <matthew.gretton-dann@arm.com>
+
* arm-dis.c (coprocessor_opcodes): Add VSEL.
(print_insn_coprocessor): Add new %<>c bitfield format
specifier.
/* FP v5. */
{FPU_VFP_EXT_ARMV8, 0xfe000a00, 0xff800f00, "vsel%20-21c%u.f32\t%y1, %y2, %y0"},
{FPU_VFP_EXT_ARMV8, 0xfe000b00, 0xff800f00, "vsel%20-21c%u.f64\t%z1, %z2, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800a00, 0xffb00f40, "vmaxnm%u.f32\t%y1, %y2, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800b00, 0xffb00f40, "vmaxnm%u.f64\t%z1, %z2, %z0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800a40, 0xffb00f40, "vminnm%u.f32\t%y1, %y2, %y0"},
+ {FPU_VFP_EXT_ARMV8, 0xfe800b40, 0xffb00f40, "vminnm%u.f64\t%z1, %z2, %z0"},
/* Generic coprocessor instructions. */
{ 0, SENTINEL_GENERIC_START, 0, "" },
{FPU_NEON_EXT_V1, 0xf3b30600, 0xffb30e10, "vcvt%c.%7-8?usff%18-19Sa.%7-8?ffus%18-19Sa\t%12-15,22R, %0-3,5R"},
/* Three registers of the same length. */
+ {FPU_NEON_EXT_ARMV8, 0xf3000f10, 0xffa00f10, "vmaxnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
+ {FPU_NEON_EXT_ARMV8, 0xf3200f10, 0xffa00f10, "vminnm%u.f%20U0\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2000110, 0xffb00f10, "vand%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2100110, 0xffb00f10, "vbic%c\t%12-15,22R, %16-19,7R, %0-3,5R"},
{FPU_NEON_EXT_V1, 0xf2200110, 0xffb00f10, "vorr%c\t%12-15,22R, %16-19,7R, %0-3,5R"},