// that the property hold, but not that it does not hold.
// Property descriptions:
- // IsSSA (currently unused, intended to eventually replace
- // MachineRegisterInfo::isSSA())
+ // IsSSA: True when the machine function is in SSA form and virtual registers
+ // have a single def.
// TracksLiveness: (currently unsued, intended to eventually replace
// MachineRegisterInfo::tracksLiveness())
// AllVRegsAllocated: All virtual registers have been allocated; i.e. all
};
private:
- const MachineFunction *MF;
+ MachineFunction *MF;
Delegate *TheDelegate;
- /// IsSSA - True when the machine function is in SSA form and virtual
- /// registers have a single def.
- bool IsSSA;
-
/// TracksLiveness - True while register liveness is being tracked accurately.
/// Basic block live-in lists, kill flags, and implicit defs may not be
/// accurate when after this flag is cleared.
MachineRegisterInfo(const MachineRegisterInfo&) = delete;
void operator=(const MachineRegisterInfo&) = delete;
public:
- explicit MachineRegisterInfo(const MachineFunction *MF);
+ explicit MachineRegisterInfo(MachineFunction *MF);
const TargetRegisterInfo *getTargetRegisterInfo() const {
return MF->getSubtarget().getRegisterInfo();
// The TwoAddressInstructionPass and PHIElimination passes take the machine
// function out of SSA form when they introduce multiple defs per virtual
// register.
- bool isSSA() const { return IsSSA; }
+ bool isSSA() const {
+ return MF->getProperties().hasProperty(
+ MachineFunctionProperties::Property::IsSSA);
+ }
// leaveSSA - Indicates that the machine function is no longer in SSA form.
- void leaveSSA() { IsSSA = false; }
+ void leaveSSA() {
+ MF->getProperties().clear(MachineFunctionProperties::Property::IsSSA);
+ }
/// tracksLiveness - Returns true when tracking register liveness accurately.
///
void MachineFunctionProperties::print(raw_ostream &ROS) const {
// Leave this function even in NDEBUG as an out-of-line anchor.
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
- if (!Properties.any()) {
- ROS << "(empty)";
- return;
- }
for (BitVector::size_type i = 0; i < Properties.size(); ++i) {
- if (Properties[i]) {
- switch(static_cast<Property>(i)) {
- case Property::AllVRegsAllocated:
- ROS << "AllVRegsAllocated ";
- break;
- default:
- // TODO: Implement IsSSA/TracksLiveness when we make them properties.
- llvm_unreachable("Unexpected value for property enum");
- }
+ bool HasProperty = Properties[i];
+ switch(static_cast<Property>(i)) {
+ case Property::IsSSA:
+ ROS << (HasProperty ? "SSA, " : "Post SSA, ");
+ break;
+ case Property::AllVRegsAllocated:
+ ROS << (HasProperty ? "AllVRegsAllocated" : "HasVRegs");
+ break;
+ default:
+ break;
}
}
#endif
unsigned FunctionNum, MachineModuleInfo &mmi)
: Fn(F), Target(TM), STI(TM.getSubtargetImpl(*F)), Ctx(mmi.getContext()),
MMI(mmi) {
+ // Assume the function starts in SSA form.
+ Properties.set(MachineFunctionProperties::Property::IsSSA);
if (STI->getRegisterInfo())
RegInfo = new (Allocator) MachineRegisterInfo(this);
else
getProperties().print(OS);
OS << "> : ";
if (RegInfo) {
- OS << (RegInfo->isSSA() ? "SSA" : "Post SSA");
if (!RegInfo->tracksLiveness())
- OS << ", not tracking liveness";
+ OS << "not tracking liveness";
}
OS << '\n';
// Pin the vtable to this file.
void MachineRegisterInfo::Delegate::anchor() {}
-MachineRegisterInfo::MachineRegisterInfo(const MachineFunction *MF)
- : MF(MF), TheDelegate(nullptr), IsSSA(true), TracksLiveness(true),
+MachineRegisterInfo::MachineRegisterInfo(MachineFunction *MF)
+ : MF(MF), TheDelegate(nullptr), TracksLiveness(true),
TracksSubRegLiveness(false) {
unsigned NumRegs = getTargetRegisterInfo()->getNumRegs();
VRegInfo.reserve(256);