drm/radeon: replace pflip and sw_int counters with atomics

So we can skip the locking. Also renames sw_int to
ring_int, cause that better matches its purpose.

Signed-off-by: Christian Koenig <christian.koenig@amd.com>

diff --git a/drivers/gpu/drm/radeon/evergreen.c b/drivers/gpu/drm/radeon/evergreen.c
index bdc1f30..f716e08 100644 (file)
--- a/drivers/gpu/drm/radeon/evergreen.c
+++ b/drivers/gpu/drm/radeon/evergreen.c
@@ -2340,20 +2340,20 @@ int evergreen_irq_set(struct radeon_device *rdev)
 
        if (rdev->family >= CHIP_CAYMAN) {
                /* enable CP interrupts on all rings */
-               if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+               if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                        DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
                        cp_int_cntl |= TIME_STAMP_INT_ENABLE;
                }
-               if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+               if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
                        DRM_DEBUG("evergreen_irq_set: sw int cp1\n");
                        cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
                }
-               if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+               if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
                        DRM_DEBUG("evergreen_irq_set: sw int cp2\n");
                        cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
                }
        } else {
-               if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+               if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                        DRM_DEBUG("evergreen_irq_set: sw int gfx\n");
                        cp_int_cntl |= RB_INT_ENABLE;
                        cp_int_cntl |= TIME_STAMP_INT_ENABLE;
@@ -2361,32 +2361,32 @@ int evergreen_irq_set(struct radeon_device *rdev)
        }
 
        if (rdev->irq.crtc_vblank_int[0] ||
-           rdev->irq.pflip[0]) {
+           atomic_read(&rdev->irq.pflip[0])) {
                DRM_DEBUG("evergreen_irq_set: vblank 0\n");
                crtc1 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[1] ||
-           rdev->irq.pflip[1]) {
+           atomic_read(&rdev->irq.pflip[1])) {
                DRM_DEBUG("evergreen_irq_set: vblank 1\n");
                crtc2 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[2] ||
-           rdev->irq.pflip[2]) {
+           atomic_read(&rdev->irq.pflip[2])) {
                DRM_DEBUG("evergreen_irq_set: vblank 2\n");
                crtc3 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[3] ||
-           rdev->irq.pflip[3]) {
+           atomic_read(&rdev->irq.pflip[3])) {
                DRM_DEBUG("evergreen_irq_set: vblank 3\n");
                crtc4 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[4] ||
-           rdev->irq.pflip[4]) {
+           atomic_read(&rdev->irq.pflip[4])) {
                DRM_DEBUG("evergreen_irq_set: vblank 4\n");
                crtc5 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[5] ||
-           rdev->irq.pflip[5]) {
+           atomic_read(&rdev->irq.pflip[5])) {
                DRM_DEBUG("evergreen_irq_set: vblank 5\n");
                crtc6 |= VBLANK_INT_MASK;
        }
@@ -2706,7 +2706,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[0])
+                                       if (atomic_read(&rdev->irq.pflip[0]))
                                                radeon_crtc_handle_flip(rdev, 0);
                                        rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D1 vblank\n");
@@ -2732,7 +2732,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[1])
+                                       if (atomic_read(&rdev->irq.pflip[1]))
                                                radeon_crtc_handle_flip(rdev, 1);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D2 vblank\n");
@@ -2758,7 +2758,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[2])
+                                       if (atomic_read(&rdev->irq.pflip[2]))
                                                radeon_crtc_handle_flip(rdev, 2);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D3 vblank\n");
@@ -2784,7 +2784,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[3])
+                                       if (atomic_read(&rdev->irq.pflip[3]))
                                                radeon_crtc_handle_flip(rdev, 3);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D4 vblank\n");
@@ -2810,7 +2810,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[4])
+                                       if (atomic_read(&rdev->irq.pflip[4]))
                                                radeon_crtc_handle_flip(rdev, 4);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D5 vblank\n");
@@ -2836,7 +2836,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[5])
+                                       if (atomic_read(&rdev->irq.pflip[5]))
                                                radeon_crtc_handle_flip(rdev, 5);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D6 vblank\n");

diff --git a/drivers/gpu/drm/radeon/r100.c b/drivers/gpu/drm/radeon/r100.c
index e8fe4ae..35825bf 100644 (file)
--- a/drivers/gpu/drm/radeon/r100.c
+++ b/drivers/gpu/drm/radeon/r100.c
@@ -689,18 +689,18 @@ int r100_irq_set(struct radeon_device *rdev)
                WREG32(R_000040_GEN_INT_CNTL, 0);
                return -EINVAL;
        }
-       if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+       if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                tmp |= RADEON_SW_INT_ENABLE;
        }
        if (rdev->irq.gui_idle) {
                tmp |= RADEON_GUI_IDLE_MASK;
        }
        if (rdev->irq.crtc_vblank_int[0] ||
-           rdev->irq.pflip[0]) {
+           atomic_read(&rdev->irq.pflip[0])) {
                tmp |= RADEON_CRTC_VBLANK_MASK;
        }
        if (rdev->irq.crtc_vblank_int[1] ||
-           rdev->irq.pflip[1]) {
+           atomic_read(&rdev->irq.pflip[1])) {
                tmp |= RADEON_CRTC2_VBLANK_MASK;
        }
        if (rdev->irq.hpd[0]) {
@@ -775,7 +775,7 @@ int r100_irq_process(struct radeon_device *rdev)
                                rdev->pm.vblank_sync = true;
                                wake_up(&rdev->irq.vblank_queue);
                        }
-                       if (rdev->irq.pflip[0])
+                       if (atomic_read(&rdev->irq.pflip[0]))
                                radeon_crtc_handle_flip(rdev, 0);
                }
                if (status & RADEON_CRTC2_VBLANK_STAT) {
@@ -784,7 +784,7 @@ int r100_irq_process(struct radeon_device *rdev)
                                rdev->pm.vblank_sync = true;
                                wake_up(&rdev->irq.vblank_queue);
                        }
-                       if (rdev->irq.pflip[1])
+                       if (atomic_read(&rdev->irq.pflip[1]))
                                radeon_crtc_handle_flip(rdev, 1);
                }
                if (status & RADEON_FP_DETECT_STAT) {

diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c
index 9cd7728..43d0c41 100644 (file)
--- a/drivers/gpu/drm/radeon/r600.c
+++ b/drivers/gpu/drm/radeon/r600.c
@@ -3025,18 +3025,18 @@ int r600_irq_set(struct radeon_device *rdev)
                hdmi1 = RREG32(HDMI1_AUDIO_PACKET_CONTROL) & ~HDMI0_AZ_FORMAT_WTRIG_MASK;
        }
 
-       if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+       if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                DRM_DEBUG("r600_irq_set: sw int\n");
                cp_int_cntl |= RB_INT_ENABLE;
                cp_int_cntl |= TIME_STAMP_INT_ENABLE;
        }
        if (rdev->irq.crtc_vblank_int[0] ||
-           rdev->irq.pflip[0]) {
+           atomic_read(&rdev->irq.pflip[0])) {
                DRM_DEBUG("r600_irq_set: vblank 0\n");
                mode_int |= D1MODE_VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[1] ||
-           rdev->irq.pflip[1]) {
+           atomic_read(&rdev->irq.pflip[1])) {
                DRM_DEBUG("r600_irq_set: vblank 1\n");
                mode_int |= D2MODE_VBLANK_INT_MASK;
        }
@@ -3334,7 +3334,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[0])
+                                       if (atomic_read(&rdev->irq.pflip[0]))
                                                radeon_crtc_handle_flip(rdev, 0);
                                        rdev->irq.stat_regs.r600.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D1 vblank\n");
@@ -3360,7 +3360,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[1])
+                                       if (atomic_read(&rdev->irq.pflip[1]))
                                                radeon_crtc_handle_flip(rdev, 1);
                                        rdev->irq.stat_regs.r600.disp_int &= ~LB_D2_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D2 vblank\n");

diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h
index 353a183..126bac5 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon.h
+++ b/drivers/gpu/drm/radeon/radeon.h
@@ -617,11 +617,9 @@ union radeon_irq_stat_regs {
 struct radeon_irq {
        bool                            installed;
        spinlock_t                      lock;
-       bool                            sw_int[RADEON_NUM_RINGS];
-       int                             sw_refcount[RADEON_NUM_RINGS];
+       atomic_t                        ring_int[RADEON_NUM_RINGS];
        bool                            crtc_vblank_int[RADEON_MAX_CRTCS];
-       bool                            pflip[RADEON_MAX_CRTCS];
-       int                             pflip_refcount[RADEON_MAX_CRTCS];
+       atomic_t                        pflip[RADEON_MAX_CRTCS];
        wait_queue_head_t               vblank_queue;
        bool                            hpd[RADEON_MAX_HPD_PINS];
        bool                            gui_idle;

diff --git a/drivers/gpu/drm/radeon/radeon_irq_kms.c b/drivers/gpu/drm/radeon/radeon_irq_kms.c
index c5eb7a1..6664514 100644 (file)
--- a/drivers/gpu/drm/radeon/radeon_irq_kms.c
+++ b/drivers/gpu/drm/radeon/radeon_irq_kms.c
@@ -70,13 +70,13 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
        spin_lock_irqsave(&rdev->irq.lock, irqflags);
        /* Disable *all* interrupts */
        for (i = 0; i < RADEON_NUM_RINGS; i++)
-               rdev->irq.sw_int[i] = false;
+               atomic_set(&rdev->irq.ring_int[i], 0);
        rdev->irq.gui_idle = false;
        for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
                rdev->irq.hpd[i] = false;
        for (i = 0; i < RADEON_MAX_CRTCS; i++) {
                rdev->irq.crtc_vblank_int[i] = false;
-               rdev->irq.pflip[i] = false;
+               atomic_set(&rdev->irq.pflip[i], 0);
                rdev->irq.afmt[i] = false;
        }
        radeon_irq_set(rdev);
@@ -87,16 +87,7 @@ void radeon_driver_irq_preinstall_kms(struct drm_device *dev)
 
 int radeon_driver_irq_postinstall_kms(struct drm_device *dev)
 {
-       struct radeon_device *rdev = dev->dev_private;
-       unsigned long irqflags;
-       unsigned i;
-
        dev->max_vblank_count = 0x001fffff;
-       spin_lock_irqsave(&rdev->irq.lock, irqflags);
-       for (i = 0; i < RADEON_NUM_RINGS; i++)
-               rdev->irq.sw_int[i] = true;
-       radeon_irq_set(rdev);
-       spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
        return 0;
 }
 
@@ -112,13 +103,13 @@ void radeon_driver_irq_uninstall_kms(struct drm_device *dev)
        spin_lock_irqsave(&rdev->irq.lock, irqflags);
        /* Disable *all* interrupts */
        for (i = 0; i < RADEON_NUM_RINGS; i++)
-               rdev->irq.sw_int[i] = false;
+               atomic_set(&rdev->irq.ring_int[i], 0);
        rdev->irq.gui_idle = false;
        for (i = 0; i < RADEON_MAX_HPD_PINS; i++)
                rdev->irq.hpd[i] = false;
        for (i = 0; i < RADEON_MAX_CRTCS; i++) {
                rdev->irq.crtc_vblank_int[i] = false;
-               rdev->irq.pflip[i] = false;
+               atomic_set(&rdev->irq.pflip[i], 0);
                rdev->irq.afmt[i] = false;
        }
        radeon_irq_set(rdev);
@@ -225,25 +216,28 @@ void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring)
 {
        unsigned long irqflags;
 
-       spin_lock_irqsave(&rdev->irq.lock, irqflags);
-       if (rdev->ddev->irq_enabled && (++rdev->irq.sw_refcount[ring] == 1)) {
-               rdev->irq.sw_int[ring] = true;
+       if (!rdev->ddev->irq_enabled)
+               return;
+
+       if (atomic_inc_return(&rdev->irq.ring_int[ring]) == 1) {
+               spin_lock_irqsave(&rdev->irq.lock, irqflags);
                radeon_irq_set(rdev);
+               spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
        }
-       spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 }
 
 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring)
 {
        unsigned long irqflags;
 
-       spin_lock_irqsave(&rdev->irq.lock, irqflags);
-       BUG_ON(rdev->ddev->irq_enabled && rdev->irq.sw_refcount[ring] <= 0);
-       if (rdev->ddev->irq_enabled && (--rdev->irq.sw_refcount[ring] == 0)) {
-               rdev->irq.sw_int[ring] = false;
+       if (!rdev->ddev->irq_enabled)
+               return;
+
+       if (atomic_dec_and_test(&rdev->irq.ring_int[ring])) {
+               spin_lock_irqsave(&rdev->irq.lock, irqflags);
                radeon_irq_set(rdev);
+               spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
        }
-       spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 }
 
 void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
@@ -253,12 +247,14 @@ void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc)
        if (crtc < 0 || crtc >= rdev->num_crtc)
                return;
 
-       spin_lock_irqsave(&rdev->irq.lock, irqflags);
-       if (rdev->ddev->irq_enabled && (++rdev->irq.pflip_refcount[crtc] == 1)) {
-               rdev->irq.pflip[crtc] = true;
+       if (!rdev->ddev->irq_enabled)
+               return;
+
+       if (atomic_inc_return(&rdev->irq.pflip[crtc]) == 1) {
+               spin_lock_irqsave(&rdev->irq.lock, irqflags);
                radeon_irq_set(rdev);
+               spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
        }
-       spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 }
 
 void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
@@ -268,13 +264,14 @@ void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc)
        if (crtc < 0 || crtc >= rdev->num_crtc)
                return;
 
-       spin_lock_irqsave(&rdev->irq.lock, irqflags);
-       BUG_ON(rdev->ddev->irq_enabled && rdev->irq.pflip_refcount[crtc] <= 0);
-       if (rdev->ddev->irq_enabled && (--rdev->irq.pflip_refcount[crtc] == 0)) {
-               rdev->irq.pflip[crtc] = false;
+       if (!rdev->ddev->irq_enabled)
+               return;
+
+       if (atomic_dec_and_test(&rdev->irq.pflip[crtc])) {
+               spin_lock_irqsave(&rdev->irq.lock, irqflags);
                radeon_irq_set(rdev);
+               spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
        }
-       spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 }
 
 void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block)

diff --git a/drivers/gpu/drm/radeon/rs600.c b/drivers/gpu/drm/radeon/rs600.c
index f9aee25..e11bc46 100644 (file)
--- a/drivers/gpu/drm/radeon/rs600.c
+++ b/drivers/gpu/drm/radeon/rs600.c
@@ -564,18 +564,18 @@ int rs600_irq_set(struct radeon_device *rdev)
                WREG32(R_000040_GEN_INT_CNTL, 0);
                return -EINVAL;
        }
-       if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+       if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                tmp |= S_000040_SW_INT_EN(1);
        }
        if (rdev->irq.gui_idle) {
                tmp |= S_000040_GUI_IDLE(1);
        }
        if (rdev->irq.crtc_vblank_int[0] ||
-           rdev->irq.pflip[0]) {
+           atomic_read(&rdev->irq.pflip[0])) {
                mode_int |= S_006540_D1MODE_VBLANK_INT_MASK(1);
        }
        if (rdev->irq.crtc_vblank_int[1] ||
-           rdev->irq.pflip[1]) {
+           atomic_read(&rdev->irq.pflip[1])) {
                mode_int |= S_006540_D2MODE_VBLANK_INT_MASK(1);
        }
        if (rdev->irq.hpd[0]) {
@@ -695,7 +695,7 @@ int rs600_irq_process(struct radeon_device *rdev)
                                rdev->pm.vblank_sync = true;
                                wake_up(&rdev->irq.vblank_queue);
                        }
-                       if (rdev->irq.pflip[0])
+                       if (atomic_read(&rdev->irq.pflip[0]))
                                radeon_crtc_handle_flip(rdev, 0);
                }
                if (G_007EDC_LB_D2_VBLANK_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {
@@ -704,7 +704,7 @@ int rs600_irq_process(struct radeon_device *rdev)
                                rdev->pm.vblank_sync = true;
                                wake_up(&rdev->irq.vblank_queue);
                        }
-                       if (rdev->irq.pflip[1])
+                       if (atomic_read(&rdev->irq.pflip[1]))
                                radeon_crtc_handle_flip(rdev, 1);
                }
                if (G_007EDC_DC_HOT_PLUG_DETECT1_INTERRUPT(rdev->irq.stat_regs.r500.disp_int)) {

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index a65045b..34603b3 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -3092,45 +3092,45 @@ int si_irq_set(struct radeon_device *rdev)
        hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
 
        /* enable CP interrupts on all rings */
-       if (rdev->irq.sw_int[RADEON_RING_TYPE_GFX_INDEX]) {
+       if (atomic_read(&rdev->irq.ring_int[RADEON_RING_TYPE_GFX_INDEX])) {
                DRM_DEBUG("si_irq_set: sw int gfx\n");
                cp_int_cntl |= TIME_STAMP_INT_ENABLE;
        }
-       if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP1_INDEX]) {
+       if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP1_INDEX])) {
                DRM_DEBUG("si_irq_set: sw int cp1\n");
                cp_int_cntl1 |= TIME_STAMP_INT_ENABLE;
        }
-       if (rdev->irq.sw_int[CAYMAN_RING_TYPE_CP2_INDEX]) {
+       if (atomic_read(&rdev->irq.ring_int[CAYMAN_RING_TYPE_CP2_INDEX])) {
                DRM_DEBUG("si_irq_set: sw int cp2\n");
                cp_int_cntl2 |= TIME_STAMP_INT_ENABLE;
        }
        if (rdev->irq.crtc_vblank_int[0] ||
-           rdev->irq.pflip[0]) {
+           atomic_read(&rdev->irq.pflip[0])) {
                DRM_DEBUG("si_irq_set: vblank 0\n");
                crtc1 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[1] ||
-           rdev->irq.pflip[1]) {
+           atomic_read(&rdev->irq.pflip[1])) {
                DRM_DEBUG("si_irq_set: vblank 1\n");
                crtc2 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[2] ||
-           rdev->irq.pflip[2]) {
+           atomic_read(&rdev->irq.pflip[2])) {
                DRM_DEBUG("si_irq_set: vblank 2\n");
                crtc3 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[3] ||
-           rdev->irq.pflip[3]) {
+           atomic_read(&rdev->irq.pflip[3])) {
                DRM_DEBUG("si_irq_set: vblank 3\n");
                crtc4 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[4] ||
-           rdev->irq.pflip[4]) {
+           atomic_read(&rdev->irq.pflip[4])) {
                DRM_DEBUG("si_irq_set: vblank 4\n");
                crtc5 |= VBLANK_INT_MASK;
        }
        if (rdev->irq.crtc_vblank_int[5] ||
-           rdev->irq.pflip[5]) {
+           atomic_read(&rdev->irq.pflip[5])) {
                DRM_DEBUG("si_irq_set: vblank 5\n");
                crtc6 |= VBLANK_INT_MASK;
        }
@@ -3396,7 +3396,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[0])
+                                       if (atomic_read(&rdev->irq.pflip[0]))
                                                radeon_crtc_handle_flip(rdev, 0);
                                        rdev->irq.stat_regs.evergreen.disp_int &= ~LB_D1_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D1 vblank\n");
@@ -3422,7 +3422,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[1])
+                                       if (atomic_read(&rdev->irq.pflip[1]))
                                                radeon_crtc_handle_flip(rdev, 1);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D2 vblank\n");
@@ -3448,7 +3448,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[2])
+                                       if (atomic_read(&rdev->irq.pflip[2]))
                                                radeon_crtc_handle_flip(rdev, 2);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D3 vblank\n");
@@ -3474,7 +3474,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[3])
+                                       if (atomic_read(&rdev->irq.pflip[3]))
                                                radeon_crtc_handle_flip(rdev, 3);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D4 vblank\n");
@@ -3500,7 +3500,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[4])
+                                       if (atomic_read(&rdev->irq.pflip[4]))
                                                radeon_crtc_handle_flip(rdev, 4);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D5 vblank\n");
@@ -3526,7 +3526,7 @@ restart_ih:
                                                rdev->pm.vblank_sync = true;
                                                wake_up(&rdev->irq.vblank_queue);
                                        }
-                                       if (rdev->irq.pflip[5])
+                                       if (atomic_read(&rdev->irq.pflip[5]))
                                                radeon_crtc_handle_flip(rdev, 5);
                                        rdev->irq.stat_regs.evergreen.disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
                                        DRM_DEBUG("IH: D6 vblank\n");