bpf, mips: Implement R4000 workarounds for JIT

For R4000 erratas around multiplication and division instructions,
as our use of those instructions are always followed by mflo/mfhi
instructions, the only issue we need care is

"MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0" Errata 28:
"A double-word or a variable shift may give an incorrect result if
executed while an integer multiplication is in progress."

We just emit a mfhi $0 to ensure the operation is completed after
every multiplication instruction according to workaround suggestion
in the document.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Acked-by: Johan Almbladh <johan.almbladh@anyfinetworks.com>
Link: https://lore.kernel.org/bpf/20230228113305.83751-3-jiaxun.yang@flygoat.com

diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index b89c4bf..363cd59 100644 (file)
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -63,9 +63,7 @@ config MIPS
        select HAVE_DEBUG_STACKOVERFLOW
        select HAVE_DMA_CONTIGUOUS
        select HAVE_DYNAMIC_FTRACE
-       select HAVE_EBPF_JIT if !CPU_MICROMIPS && \
-                               !CPU_R4000_WORKAROUNDS && \
-                               !CPU_R4400_WORKAROUNDS
+       select HAVE_EBPF_JIT if !CPU_MICROMIPS
        select HAVE_EXIT_THREAD
        select HAVE_FAST_GUP
        select HAVE_FTRACE_MCOUNT_RECORD

diff --git a/arch/mips/net/bpf_jit_comp64.c b/arch/mips/net/bpf_jit_comp64.c
index 0e7c1bd..fa7e9aa 100644 (file)
--- a/arch/mips/net/bpf_jit_comp64.c
+++ b/arch/mips/net/bpf_jit_comp64.c
@@ -228,6 +228,9 @@ static void emit_alu_r64(struct jit_context *ctx, u8 dst, u8 src, u8 op)
                } else {
                        emit(ctx, dmultu, dst, src);
                        emit(ctx, mflo, dst);
+                       /* Ensure multiplication is completed */
+                       if (IS_ENABLED(CONFIG_CPU_R4000_WORKAROUNDS))
+                               emit(ctx, mfhi, MIPS_R_ZERO);
                }
                break;
        /* dst = dst / src */