case PIPE_SHADER_CAP_MAX_CONSTS:
return R600_MAX_CONST_BUFFER_SIZE;
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
- return R600_MAX_CONST_BUFFERS-1;
+ return R600_MAX_USER_CONST_BUFFERS;
case PIPE_SHADER_CAP_MAX_PREDS:
return 0; /* nothing uses this */
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
#define R600_NUM_ATOMS 36
-#define R600_MAX_CONST_BUFFERS 2
+#define R600_MAX_USER_CONST_BUFFERS 1
+#define R600_MAX_DRIVER_CONST_BUFFERS 1
+#define R600_MAX_CONST_BUFFERS (R600_MAX_USER_CONST_BUFFERS + R600_MAX_DRIVER_CONST_BUFFERS)
+
+/* start driver buffers after user buffers */
+#define R600_UCP_CONST_BUFFER (R600_MAX_USER_CONST_BUFFERS)
+
#define R600_MAX_CONST_BUFFER_SIZE 4096
#ifdef PIPE_ARCH_BIG_ENDIAN
alu.src[0].chan = j;
alu.src[1].sel = 512 + i;
- alu.src[1].kc_bank = 1;
+ alu.src[1].kc_bank = R600_UCP_CONST_BUFFER;
alu.src[1].chan = j;
alu.dst.sel = ctx.temp_reg + oreg;
cb.user_buffer = state->ucp;
cb.buffer_offset = 0;
cb.buffer_size = 4*4*8;
- ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, 1, &cb);
+ ctx->set_constant_buffer(ctx, PIPE_SHADER_VERTEX, R600_UCP_CONST_BUFFER, &cb);
pipe_resource_reference(&cb.buffer, NULL);
}