drm/nouveau/fifo: use type+inst to determine context pointer offsets
authorBen Skeggs <bskeggs@redhat.com>
Sat, 6 Feb 2021 11:39:41 +0000 (21:39 +1000)
committerBen Skeggs <bskeggs@redhat.com>
Thu, 11 Feb 2021 01:49:57 +0000 (11:49 +1000)
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
drivers/gpu/drm/nouveau/nvkm/engine/fifo/chang84.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/channv50.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv04.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/dmanv40.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogf100.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogk104.c
drivers/gpu/drm/nouveau/nvkm/engine/fifo/gpfifogv100.c

index b298b05..353b77d 100644 (file)
@@ -47,7 +47,7 @@ g84_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
 static int
 g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
 {
-       switch (engine->subdev.index) {
+       switch (engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW    : return -1;
        case NVKM_ENGINE_GR    : return 0x0020;
@@ -59,7 +59,7 @@ g84_fifo_chan_engine_addr(struct nvkm_engine *engine)
        case NVKM_ENGINE_MSVLD : return 0x0080;
        case NVKM_ENGINE_CIPHER:
        case NVKM_ENGINE_SEC   : return 0x00a0;
-       case NVKM_ENGINE_CE0   : return 0x00c0;
+       case NVKM_ENGINE_CE    : return 0x00c0;
        default:
                WARN_ON(1);
                return -1;
@@ -157,14 +157,14 @@ g84_fifo_chan_object_ctor(struct nvkm_fifo_chan *base,
        u32 handle = object->handle;
        u32 context;
 
-       switch (object->engine->subdev.index) {
+       switch (object->engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW    : context = 0x00000000; break;
        case NVKM_ENGINE_GR    : context = 0x00100000; break;
        case NVKM_ENGINE_MPEG  :
        case NVKM_ENGINE_MSPPP : context = 0x00200000; break;
        case NVKM_ENGINE_ME    :
-       case NVKM_ENGINE_CE0   : context = 0x00300000; break;
+       case NVKM_ENGINE_CE    : context = 0x00300000; break;
        case NVKM_ENGINE_VP    :
        case NVKM_ENGINE_MSPDEC: context = 0x00400000; break;
        case NVKM_ENGINE_CIPHER:
index c314d9a..c44d7c8 100644 (file)
@@ -31,7 +31,7 @@
 static int
 nv50_fifo_chan_engine_addr(struct nvkm_engine *engine)
 {
-       switch (engine->subdev.index) {
+       switch (engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW    : return -1;
        case NVKM_ENGINE_GR    : return 0x0000;
@@ -170,7 +170,7 @@ nv50_fifo_chan_object_ctor(struct nvkm_fifo_chan *base,
        u32 handle = object->handle;
        u32 context;
 
-       switch (object->engine->subdev.index) {
+       switch (object->engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW    : context = 0x00000000; break;
        case NVKM_ENGINE_GR    : context = 0x00100000; break;
index b19a2bd..dbcdc5f 100644 (file)
@@ -53,7 +53,7 @@ nv04_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
        u32 handle  = object->handle;
        int hash;
 
-       switch (object->engine->subdev.index) {
+       switch (object->engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW    : context |= 0x00000000; break;
        case NVKM_ENGINE_GR    : context |= 0x00010000; break;
index 9c32746..0411fb9 100644 (file)
@@ -35,7 +35,7 @@
 static bool
 nv40_fifo_dma_engine(struct nvkm_engine *engine, u32 *reg, u32 *ctx)
 {
-       switch (engine->subdev.index) {
+       switch (engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW:
                return false;
@@ -157,7 +157,7 @@ nv40_fifo_dma_object_ctor(struct nvkm_fifo_chan *base,
        u32 handle  = object->handle;
        int hash;
 
-       switch (object->engine->subdev.index) {
+       switch (object->engine->subdev.type) {
        case NVKM_ENGINE_DMAOBJ:
        case NVKM_ENGINE_SW    : context |= 0x00000000; break;
        case NVKM_ENGINE_GR    : context |= 0x00100000; break;
index 1ebfbd7..4e78bbe 100644 (file)
@@ -52,11 +52,10 @@ gf100_fifo_chan_ntfy(struct nvkm_fifo_chan *chan, u32 type,
 static u32
 gf100_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
 {
-       switch (engine->subdev.index) {
+       switch (engine->subdev.type) {
        case NVKM_ENGINE_SW    : return 0;
        case NVKM_ENGINE_GR    : return 0x0210;
-       case NVKM_ENGINE_CE0   : return 0x0230;
-       case NVKM_ENGINE_CE1   : return 0x0240;
+       case NVKM_ENGINE_CE    : return 0x0230 + (engine->subdev.inst * 0x10);
        case NVKM_ENGINE_MSPDEC: return 0x0250;
        case NVKM_ENGINE_MSPPP : return 0x0260;
        case NVKM_ENGINE_MSVLD : return 0x0270;
index 8cedbc7..b6900a5 100644 (file)
@@ -74,10 +74,9 @@ gk104_fifo_gpfifo_kick(struct gk104_fifo_chan *chan)
 static u32
 gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
 {
-       switch (engine->subdev.index) {
+       switch (engine->subdev.type) {
        case NVKM_ENGINE_SW    :
-       case NVKM_ENGINE_CE0...NVKM_ENGINE_CE_LAST:
-               return 0;
+       case NVKM_ENGINE_CE    : return 0;
        case NVKM_ENGINE_GR    : return 0x0210;
        case NVKM_ENGINE_SEC   : return 0x0220;
        case NVKM_ENGINE_MSPDEC: return 0x0250;
@@ -85,9 +84,11 @@ gk104_fifo_gpfifo_engine_addr(struct nvkm_engine *engine)
        case NVKM_ENGINE_MSVLD : return 0x0270;
        case NVKM_ENGINE_VIC   : return 0x0280;
        case NVKM_ENGINE_MSENC : return 0x0290;
-       case NVKM_ENGINE_NVDEC0: return 0x02100270;
-       case NVKM_ENGINE_NVENC0: return 0x02100290;
-       case NVKM_ENGINE_NVENC1: return 0x0210;
+       case NVKM_ENGINE_NVDEC : return 0x02100270;
+       case NVKM_ENGINE_NVENC :
+               if (engine->subdev.inst)
+                       return 0x0210;
+               return 0x02100290;
        default:
                WARN_ON(1);
                return 0;
index aaae4d8..ee4967b 100644 (file)
@@ -70,8 +70,7 @@ gv100_fifo_gpfifo_engine_fini(struct nvkm_fifo_chan *base,
        struct nvkm_gpuobj *inst = chan->base.inst;
        int ret;
 
-       if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
-           engine->subdev.index <= NVKM_ENGINE_CE_LAST)
+       if (engine->subdev.type == NVKM_ENGINE_CE)
                return gk104_fifo_gpfifo_kick(chan);
 
        ret = gv100_fifo_gpfifo_engine_valid(chan, false, false);
@@ -93,8 +92,7 @@ gv100_fifo_gpfifo_engine_init(struct nvkm_fifo_chan *base,
        struct gk104_fifo_engn *engn = gk104_fifo_gpfifo_engine(chan, engine);
        struct nvkm_gpuobj *inst = chan->base.inst;
 
-       if (engine->subdev.index >= NVKM_ENGINE_CE0 &&
-           engine->subdev.index <= NVKM_ENGINE_CE_LAST)
+       if (engine->subdev.type == NVKM_ENGINE_CE)
                return 0;
 
        nvkm_kmap(inst);