drm/amdgpu: Consolidate RAS cmd warning messages

Explicity post warning if cmd is issued against unsupported IP

Update to latest RAS TA interface

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
index 7d09b28..55ffc3d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
@@ -1311,6 +1311,11 @@ int psp_ras_invoke(struct psp_context *psp, uint32_t ta_cmd_id)
                else if (ras_cmd->ras_out_message.flags.reg_access_failure_flag)
                        dev_warn(psp->adev->dev,
                                 "RAS internal register access blocked\n");
+
+               if (ras_cmd->ras_status == TA_RAS_STATUS__ERROR_UNSUPPORTED_IP)
+                   dev_warn(psp->adev->dev, "RAS WARNING: cmd failed due to unsupported ip\n");
+               else if (ras_cmd->ras_status)
+                   dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
        }
 
        return ret;
@@ -1339,9 +1344,6 @@ int psp_ras_enable_features(struct psp_context *psp,
        if (ret)
                return -EINVAL;
 
-       if (ras_cmd->ras_status)
-               dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
-
        return 0;
 }
 
@@ -1484,10 +1486,8 @@ int psp_ras_trigger_error(struct psp_context *psp,
        if (amdgpu_ras_intr_triggered())
                return 0;
 
-       if (ras_cmd->ras_status) {
-               dev_warn(psp->adev->dev, "RAS WARNING: ras status = 0x%X\n", ras_cmd->ras_status);
+       if (ras_cmd->ras_status)
                return -EINVAL;
-       }
 
        return 0;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
index 82d956d..de24a0a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
+++ b/drivers/gpu/drm/amd/amdgpu/ta_ras_if.h
@@ -38,9 +38,8 @@ enum ras_command {
        TA_RAS_COMMAND__TRIGGER_ERROR,
 };
 
-enum ta_ras_status
-{
-       TA_RAS_STATUS__SUCCESS                          = 0x00,
+enum ta_ras_status {
+       TA_RAS_STATUS__SUCCESS                          = 0x0000,
        TA_RAS_STATUS__RESET_NEEDED                     = 0xA001,
        TA_RAS_STATUS__ERROR_INVALID_PARAMETER          = 0xA002,
        TA_RAS_STATUS__ERROR_RAS_NOT_AVAILABLE          = 0xA003,
@@ -55,7 +54,12 @@ enum ta_ras_status
        TA_RAS_STATUS__ERROR_GET_DEV_INFO               = 0xA00C,
        TA_RAS_STATUS__ERROR_UNSUPPORTED_DEV            = 0xA00D,
        TA_RAS_STATUS__ERROR_NOT_INITIALIZED            = 0xA00E,
-       TA_RAS_STATUS__ERROR_TEE_INTERNAL               = 0xA00F
+       TA_RAS_STATUS__ERROR_TEE_INTERNAL               = 0xA00F,
+       TA_RAS_STATUS__ERROR_UNSUPPORTED_FUNCTION       = 0xA010,
+       TA_RAS_STATUS__ERROR_SYS_DRV_REG_ACCESS         = 0xA011,
+       TA_RAS_STATUS__ERROR_RAS_READ_WRITE             = 0xA012,
+       TA_RAS_STATUS__ERROR_NULL_PTR                   = 0xA013,
+       TA_RAS_STATUS__ERROR_UNSUPPORTED_IP             = 0xA014
 };
 
 enum ta_ras_block {
@@ -77,8 +81,7 @@ enum ta_ras_block {
        TA_NUM_BLOCK_MAX
 };
 
-enum ta_ras_mca_block
-{
+enum ta_ras_mca_block {
        TA_RAS_MCA_BLOCK__MP0   = 0,
        TA_RAS_MCA_BLOCK__MP1   = 1,
        TA_RAS_MCA_BLOCK__MPIO  = 2,
@@ -115,17 +118,15 @@ struct ta_ras_trigger_error_input {
        uint64_t                value;                  // method if error injection. i.e persistent, coherent etc.
 };
 
-struct ta_ras_init_flags
-{
-    uint8_t     poison_mode_en;
-    uint8_t     dgpu_mode;
+struct ta_ras_init_flags {
+       uint8_t poison_mode_en;
+       uint8_t dgpu_mode;
 };
 
-struct ta_ras_output_flags
-{
-       uint8_t    ras_init_success_flag;
-       uint8_t    err_inject_switch_disable_flag;
-       uint8_t    reg_access_failure_flag;
+struct ta_ras_output_flags {
+       uint8_t ras_init_success_flag;
+       uint8_t err_inject_switch_disable_flag;
+       uint8_t reg_access_failure_flag;
 };
 
 /* Common input structure for RAS callbacks */
@@ -136,14 +137,13 @@ union ta_ras_cmd_input {
        struct ta_ras_disable_features_input    disable_features;
        struct ta_ras_trigger_error_input       trigger_error;
 
-       uint32_t        reserve_pad[256];
+       uint32_t reserve_pad[256];
 };
 
-union ta_ras_cmd_output
-{
-       struct ta_ras_output_flags  flags;
+union ta_ras_cmd_output {
+       struct ta_ras_output_flags flags;
 
-       uint32_t        reserve_pad[256];
+       uint32_t reserve_pad[256];
 };
 
 /* Shared Memory structures */