wifi: rtw89: add to dump TX FIFO 0/1 for 8852C
authorPing-Ke Shih <pkshih@realtek.com>
Fri, 30 Sep 2022 13:44:17 +0000 (21:44 +0800)
committerKalle Valo <kvalo@kernel.org>
Wed, 5 Oct 2022 07:43:19 +0000 (10:43 +0300)
MAC maintains TX FIFO to transmit packets with meta data to BB layer. To
debug abnormal transmission, we need to dump the content to dig problem.
Since FIFO of 8852C locates on different address with different size and
need additional switch to enable read operation, this patch adds the
changes accordingly.

Signed-off-by: Ping-Ke Shih <pkshih@realtek.com>
Signed-off-by: Kalle Valo <kvalo@kernel.org>
Link: https://lore.kernel.org/r/20220930134417.10282-2-pkshih@realtek.com
drivers/net/wireless/realtek/rtw89/debug.c
drivers/net/wireless/realtek/rtw89/mac.c
drivers/net/wireless/realtek/rtw89/mac.h

index f584fa5..8f27c88 100644 (file)
@@ -774,13 +774,34 @@ rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
 {
        struct rtw89_debugfs_priv *debugfs_priv = m->private;
        struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
+       bool grant_read = false;
+
+       if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
+               return -ENOENT;
+
+       if (rtwdev->chip->chip_id == RTL8852C) {
+               switch (debugfs_priv->mac_mem.sel) {
+               case RTW89_MAC_MEM_TXD_FIFO_0_V1:
+               case RTW89_MAC_MEM_TXD_FIFO_1_V1:
+               case RTW89_MAC_MEM_TXDATA_FIFO_0:
+               case RTW89_MAC_MEM_TXDATA_FIFO_1:
+                       grant_read = true;
+                       break;
+               default:
+                       break;
+               }
+       }
 
        mutex_lock(&rtwdev->mutex);
        rtw89_leave_ps_mode(rtwdev);
+       if (grant_read)
+               rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
        rtw89_debug_dump_mac_mem(m, rtwdev,
                                 debugfs_priv->mac_mem.sel,
                                 debugfs_priv->mac_mem.start,
                                 debugfs_priv->mac_mem.len);
+       if (grant_read)
+               rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
        mutex_unlock(&rtwdev->mutex);
 
        return 0;
index 878c33f..3531a85 100644 (file)
@@ -31,6 +31,8 @@ const u32 rtw89_mac_mem_base_addrs[RTW89_MAC_MEM_NUM] = {
        [RTW89_MAC_MEM_TXDATA_FIFO_1]   = TXDATA_FIFO_1_BASE_ADDR,
        [RTW89_MAC_MEM_CPU_LOCAL]       = CPU_LOCAL_BASE_ADDR,
        [RTW89_MAC_MEM_BSSID_CAM]       = BSSID_CAM_BASE_ADDR,
+       [RTW89_MAC_MEM_TXD_FIFO_0_V1]   = TXD_FIFO_0_BASE_ADDR_V1,
+       [RTW89_MAC_MEM_TXD_FIFO_1_V1]   = TXD_FIFO_1_BASE_ADDR_V1,
 };
 
 static void rtw89_mac_mem_write(struct rtw89_dev *rtwdev, u32 offset,
index 6f4ada1..a9867ac 100644 (file)
@@ -245,6 +245,8 @@ enum rtw89_mac_dbg_port_sel {
 #define        BCN_IE_CAM1_BASE_ADDR           0x188A0000
 #define        TXD_FIFO_0_BASE_ADDR            0x18856200
 #define        TXD_FIFO_1_BASE_ADDR            0x188A1080
+#define        TXD_FIFO_0_BASE_ADDR_V1         0x18856400 /* for 8852C */
+#define        TXD_FIFO_1_BASE_ADDR_V1         0x188A1080 /* for 8852C */
 #define        TXDATA_FIFO_0_BASE_ADDR         0x18856000
 #define        TXDATA_FIFO_1_BASE_ADDR         0x188A1000
 #define        CPU_LOCAL_BASE_ADDR             0x18003000
@@ -271,6 +273,8 @@ enum rtw89_mac_mem_sel {
        RTW89_MAC_MEM_TXDATA_FIFO_1,
        RTW89_MAC_MEM_CPU_LOCAL,
        RTW89_MAC_MEM_BSSID_CAM,
+       RTW89_MAC_MEM_TXD_FIFO_0_V1,
+       RTW89_MAC_MEM_TXD_FIFO_1_V1,
 
        /* keep last */
        RTW89_MAC_MEM_NUM,