85xx: Add setting of cache props in the device tree.

Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c
index bb87740..92952e6 100644 (file)
--- a/cpu/mpc85xx/fdt.c
+++ b/cpu/mpc85xx/fdt.c
@@ -26,6 +26,7 @@
 #include <common.h>
 #include <libfdt.h>
 #include <fdt_support.h>
+#include <asm/processor.h>
 
 extern void ft_qe_setup(void *blob);
 #ifdef CONFIG_MP
@@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit)
 }
 #endif
 
+#ifdef CONFIG_L2_CACHE
+/* return size in kilobytes */
+static inline u32 l2cache_size(void)
+{
+       volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR;
+       volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3;
+       u32 ver = SVR_SOC_VER(get_svr());
+
+       switch (l2siz_field) {
+       case 0x0:
+               break;
+       case 0x1:
+               if (ver == SVR_8540 || ver == SVR_8560   ||
+                   ver == SVR_8541 || ver == SVR_8541_E ||
+                   ver == SVR_8555 || ver == SVR_8555_E)
+                       return 128;
+               else
+                       return 256;
+               break;
+       case 0x2:
+               if (ver == SVR_8540 || ver == SVR_8560   ||
+                   ver == SVR_8541 || ver == SVR_8541_E ||
+                   ver == SVR_8555 || ver == SVR_8555_E)
+                       return 256;
+               else
+                       return 512;
+               break;
+       case 0x3:
+               return 1024;
+               break;
+       }
+
+       return 0;
+}
+
+static inline void ft_fixup_l2cache(void *blob)
+{
+       int len, off;
+       u32 *ph;
+       struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr()));
+       char compat_buf[38];
+
+       const u32 line_size = 32;
+       const u32 num_ways = 8;
+       const u32 size = l2cache_size() * 1024;
+       const u32 num_sets = size / (line_size * num_ways);
+
+       off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+       if (off < 0) {
+               debug("no cpu node fount\n");
+               return;
+       }
+
+       ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0);
+
+       if (ph == NULL) {
+               debug("no next-level-cache property\n");
+               return ;
+       }
+
+       off = fdt_node_offset_by_phandle(blob, *ph);
+       if (off < 0) {
+               printf("%s: %s\n", __func__, fdt_strerror(off));
+               return ;
+       }
+
+       if (cpu) {
+               len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller",
+                               cpu->name);
+               sprintf(&compat_buf[len + 1], "cache");
+       }
+       fdt_setprop(blob, off, "cache-unified", NULL, 0);
+       fdt_setprop_cell(blob, off, "cache-block-size", line_size);
+       fdt_setprop_cell(blob, off, "cache-line-size", line_size);
+       fdt_setprop_cell(blob, off, "cache-size", size);
+       fdt_setprop_cell(blob, off, "cache-sets", num_sets);
+       fdt_setprop_cell(blob, off, "cache-level", 2);
+       fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf));
+}
+#else
+#define ft_fixup_l2cache(x)
+#endif
+
+static inline void ft_fixup_cache(void *blob)
+{
+       int off;
+
+       off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
+
+       while (off != -FDT_ERR_NOTFOUND) {
+               u32 l1cfg0 = mfspr(SPRN_L1CFG0);
+               u32 l1cfg1 = mfspr(SPRN_L1CFG1);
+               u32 isize, iline_size, inum_sets, inum_ways;
+               u32 dsize, dline_size, dnum_sets, dnum_ways;
+
+               /* d-side config */
+               dsize = (l1cfg0 & 0x7ff) * 1024;
+               dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1;
+               dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32;
+               dnum_sets = dsize / (dline_size * dnum_ways);
+
+               fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size);
+               fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size);
+               fdt_setprop_cell(blob, off, "d-cache-size", dsize);
+               fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets);
+
+               /* i-side config */
+               isize = (l1cfg1 & 0x7ff) * 1024;
+               inum_ways = ((l1cfg1 >> 11) & 0xff) + 1;
+               iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32;
+               inum_sets = isize / (iline_size * inum_ways);
+
+               fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size);
+               fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size);
+               fdt_setprop_cell(blob, off, "i-cache-size", isize);
+               fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets);
+
+               off = fdt_node_offset_by_prop_value(blob, off,
+                               "device_type", "cpu", 4);
+       }
+
+       ft_fixup_l2cache(blob);
+}
+
+
 void ft_cpu_setup(void *blob, bd_t *bd)
 {
 #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\
@@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd)
 #ifdef CONFIG_MP
        ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize);
 #endif
+
+       ft_fixup_cache(blob);
 }