stmmac: intel: add phy-mode and fixed-link ACPI _DSD setting support

Currently, phy_interface for TSN controller instance is set based on its
PCI Device ID. For SGMII PHY interface, phy_interface default to
PHY_INTERFACE_MODE_SGMII. As C37 AN supports both SGMII and 1000BASE-X
mode, we add support for 'phy-mode' ACPI _DSD for port-specific
and customer platform specific customization.

v3: use fwnode_get_phy_mode() as suggested by Andrew Lunn in
https://patchwork.kernel.org/comment/24895330/

v2:
For platform that sets 'fixed-link' using ACPI _DSD, we will unset
xpcs_an_inband within stmmac. Thanks to Russell King for his comment in
https://patchwork.kernel.org/comment/24890222/

v1:
Thanks to Andrew Lunn's guidance in
https://patchwork.kernel.org/comment/24827101/

Tested-by: Emilio Riva <emilio.riva@ericsson.com>
Signed-off-by: Ong Boon Leong <boon.leong.ong@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
index 675dfb8..d0e82cb 100644 (file)
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-intel.c
@@ -442,6 +442,7 @@ static void common_default_data(struct plat_stmmacenet_data *plat)
 static int intel_mgbe_common_data(struct pci_dev *pdev,
                                  struct plat_stmmacenet_data *plat)
 {
+       struct fwnode_handle *fwnode;
        char clk_name[20];
        int ret;
        int i;
@@ -560,6 +561,24 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
        /* Use the last Rx queue */
        plat->vlan_fail_q = plat->rx_queues_to_use - 1;
 
+       /* For fixed-link setup, we allow phy-mode setting */
+       fwnode = dev_fwnode(&pdev->dev);
+       if (fwnode) {
+               int phy_mode;
+
+               /* "phy-mode" setting is optional. If it is set,
+                *  we allow either sgmii or 1000base-x for now.
+                */
+               phy_mode = fwnode_get_phy_mode(fwnode);
+               if (phy_mode >= 0) {
+                       if (phy_mode == PHY_INTERFACE_MODE_SGMII ||
+                           phy_mode == PHY_INTERFACE_MODE_1000BASEX)
+                               plat->phy_interface = phy_mode;
+                       else
+                               dev_warn(&pdev->dev, "Invalid phy-mode\n");
+               }
+       }
+
        /* Intel mgbe SGMII interface uses pcs-xcps */
        if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII ||
            plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) {
@@ -567,6 +586,17 @@ static int intel_mgbe_common_data(struct pci_dev *pdev,
                plat->mdio_bus_data->xpcs_an_inband = true;
        }
 
+       /* For fixed-link setup, we clear xpcs_an_inband */
+       if (fwnode) {
+               struct fwnode_handle *fixed_node;
+
+               fixed_node = fwnode_get_named_child_node(fwnode, "fixed-link");
+               if (fixed_node)
+                       plat->mdio_bus_data->xpcs_an_inband = false;
+
+               fwnode_handle_put(fixed_node);
+       }
+
        /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */
        plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR;
        plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR;