memory: tegra: Add Tegra234 support
authorThierry Reding <treding@nvidia.com>
Fri, 6 May 2022 13:23:09 +0000 (15:23 +0200)
committerKrzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Mon, 9 May 2022 08:46:00 +0000 (10:46 +0200)
The memory controller and external memory controller found on Tegra234
is similar to the version found on earlier SoCs but supports a number of
new memory clients.

Add initial memory client definitions for the Tegra234 so that the SMMU
stream ID override registers can be properly programmed at boot time.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Link: https://lore.kernel.org/r/20220506132312.3910637-2-thierry.reding@gmail.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
drivers/memory/tegra/Makefile
drivers/memory/tegra/mc.c
drivers/memory/tegra/mc.h
drivers/memory/tegra/tegra186-emc.c
drivers/memory/tegra/tegra234.c [new file with mode: 0644]

index c992e87..0750847 100644 (file)
@@ -9,6 +9,7 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_132_SOC) += tegra124.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
 tegra-mc-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186.o tegra194.o
+tegra-mc-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186.o tegra234.o
 
 obj-$(CONFIG_TEGRA_MC) += tegra-mc.o
 
@@ -19,5 +20,6 @@ obj-$(CONFIG_TEGRA210_EMC_TABLE) += tegra210-emc-table.o
 obj-$(CONFIG_TEGRA210_EMC) += tegra210-emc.o
 obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186-emc.o
 obj-$(CONFIG_ARCH_TEGRA_194_SOC) += tegra186-emc.o
+obj-$(CONFIG_ARCH_TEGRA_234_SOC) += tegra186-emc.o
 
 tegra210-emc-y := tegra210-emc-core.o tegra210-emc-cc-r21021.o
index 44b4a40..bf3abb6 100644 (file)
@@ -45,6 +45,9 @@ static const struct of_device_id tegra_mc_of_match[] = {
 #ifdef CONFIG_ARCH_TEGRA_194_SOC
        { .compatible = "nvidia,tegra194-mc", .data = &tegra194_mc_soc },
 #endif
+#ifdef CONFIG_ARCH_TEGRA_234_SOC
+       { .compatible = "nvidia,tegra234-mc", .data = &tegra234_mc_soc },
+#endif
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, tegra_mc_of_match);
index 1e49298..062886e 100644 (file)
@@ -137,6 +137,10 @@ extern const struct tegra_mc_soc tegra186_mc_soc;
 extern const struct tegra_mc_soc tegra194_mc_soc;
 #endif
 
+#ifdef CONFIG_ARCH_TEGRA_234_SOC
+extern const struct tegra_mc_soc tegra234_mc_soc;
+#endif
+
 #if defined(CONFIG_ARCH_TEGRA_3x_SOC) || \
     defined(CONFIG_ARCH_TEGRA_114_SOC) || \
     defined(CONFIG_ARCH_TEGRA_124_SOC) || \
@@ -147,7 +151,8 @@ extern const struct tegra_mc_ops tegra30_mc_ops;
 #endif
 
 #if defined(CONFIG_ARCH_TEGRA_186_SOC) || \
-    defined(CONFIG_ARCH_TEGRA_194_SOC)
+    defined(CONFIG_ARCH_TEGRA_194_SOC) || \
+    defined(CONFIG_ARCH_TEGRA_234_SOC)
 extern const struct tegra_mc_ops tegra186_mc_ops;
 #endif
 
index 746c4ef..54b47ca 100644 (file)
@@ -273,6 +273,9 @@ static const struct of_device_id tegra186_emc_of_match[] = {
 #if defined(CONFIG_ARCH_TEGRA_194_SOC)
        { .compatible = "nvidia,tegra194-emc" },
 #endif
+#if defined(CONFIG_ARCH_TEGRA_234_SOC)
+       { .compatible = "nvidia,tegra234-emc" },
+#endif
        { /* sentinel */ }
 };
 MODULE_DEVICE_TABLE(of, tegra186_emc_of_match);
diff --git a/drivers/memory/tegra/tegra234.c b/drivers/memory/tegra/tegra234.c
new file mode 100644 (file)
index 0000000..45efc51
--- /dev/null
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2021 NVIDIA CORPORATION.  All rights reserved.
+ */
+
+#include <soc/tegra/mc.h>
+
+#include <dt-bindings/memory/tegra234-mc.h>
+
+#include "mc.h"
+
+static const struct tegra_mc_client tegra234_mc_clients[] = {
+       {
+               .id = TEGRA234_MEMORY_CLIENT_SDMMCRAB,
+               .name = "sdmmcrab",
+               .sid = TEGRA234_SID_SDMMC4,
+               .regs = {
+                       .sid = {
+                               .override = 0x318,
+                               .security = 0x31c,
+                       },
+               },
+       }, {
+               .id = TEGRA234_MEMORY_CLIENT_SDMMCWAB,
+               .name = "sdmmcwab",
+               .sid = TEGRA234_SID_SDMMC4,
+               .regs = {
+                       .sid = {
+                               .override = 0x338,
+                               .security = 0x33c,
+                       },
+               },
+       }, {
+               .id = TEGRA234_MEMORY_CLIENT_BPMPR,
+               .name = "bpmpr",
+               .sid = TEGRA234_SID_BPMP,
+               .regs = {
+                       .sid = {
+                               .override = 0x498,
+                               .security = 0x49c,
+                       },
+               },
+       }, {
+               .id = TEGRA234_MEMORY_CLIENT_BPMPW,
+               .name = "bpmpw",
+               .sid = TEGRA234_SID_BPMP,
+               .regs = {
+                       .sid = {
+                               .override = 0x4a0,
+                               .security = 0x4a4,
+                       },
+               },
+       }, {
+               .id = TEGRA234_MEMORY_CLIENT_BPMPDMAR,
+               .name = "bpmpdmar",
+               .sid = TEGRA234_SID_BPMP,
+               .regs = {
+                       .sid = {
+                               .override = 0x4a8,
+                               .security = 0x4ac,
+                       },
+               },
+       }, {
+               .id = TEGRA234_MEMORY_CLIENT_BPMPDMAW,
+               .name = "bpmpdmaw",
+               .sid = TEGRA234_SID_BPMP,
+               .regs = {
+                       .sid = {
+                               .override = 0x4b0,
+                               .security = 0x4b4,
+                       },
+               },
+       },
+};
+
+const struct tegra_mc_soc tegra234_mc_soc = {
+       .num_clients = ARRAY_SIZE(tegra234_mc_clients),
+       .clients = tegra234_mc_clients,
+       .num_address_bits = 40,
+       .ops = &tegra186_mc_ops,
+};