[AArch64][GlobalISel] Replace explicit vreg creation with implicit using SrcOp. NFC.

llvm-svn: 368653

diff --git a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
index 4df68fd1f451ed3a07286a0a54f97a772fed1088..d19e0c1592b0cbab92e4eeace4f7d89d414b94dc 100644 (file)
--- a/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
+++ b/llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp
@@ -2384,13 +2384,14 @@ bool AArch64InstructionSelector::selectTLSGlobalValue(
   MIB.buildInstr(AArch64::LOADgot, {AArch64::X0}, {})
       .addGlobalAddress(&GV, 0, AArch64II::MO_TLS);
 
-  Register DestReg = MRI.createVirtualRegister(&AArch64::GPR64commonRegClass);
-  MIB.buildInstr(AArch64::LDRXui, {DestReg}, {Register(AArch64::X0)}).addImm(0);
+  auto Load = MIB.buildInstr(AArch64::LDRXui, {&AArch64::GPR64commonRegClass},
+                             {Register(AArch64::X0)})
+                  .addImm(0);
 
   // TLS calls preserve all registers except those that absolutely must be
   // trashed: X0 (it takes an argument), LR (it's a call) and NZCV (let's not be
   // silly).
-  MIB.buildInstr(AArch64::BLR, {}, {DestReg})
+  MIB.buildInstr(AArch64::BLR, {}, {Load})
       .addDef(AArch64::X0, RegState::Implicit)
       .addRegMask(TRI.getTLSCallPreservedMask());