arm64: dts: ti: k3-j721e: Configure pinctrl for timer IO

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.

The multiplexing is documented in Technical Reference Manual[1] under
"Timer IO Muxing Control Registers" and "Timer IO Muxing Control
Registers", and the "Timers Overview" chapters.

We do not expose the cascade_en bit due to the racy usage of
independent 32 bit registers in-line with the timer instantiation in
the device tree. The MCU timer controls are also marked as reserved for
usage by the MCU firmware.

[1] http://www.ti.com/lit/pdf/spruil1

Signed-off-by: Nishanth Menon <nm@ti.com>
Reviewed-by: Tony Lindgren <tony@atomide.com>
Link: https://lore.kernel.org/r/20230531213215.602395-3-nm@ti.com
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
index 784cce4..a40d34f 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-main.dtsi
@@ -548,6 +548,24 @@
                pinctrl-single,function-mask = <0xffffffff>;
        };
 
+       /* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+       main_timerio_input: pinctrl@104200 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x104200 0x00 0x50>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x00000007>;
+       };
+
+       /* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+       main_timerio_output: pinctrl@104280 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x104280 0x00 0x20>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x0000001f>;
+       };
+
        serdes_wiz0: wiz@5000000 {
                compatible = "ti,j721e-wiz-16g";
                #address-cells = <1>;

diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
index edad335..ea5b9e1 100644 (file)
--- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi
@@ -62,6 +62,28 @@
                pinctrl-single,function-mask = <0xffffffff>;
        };
 
+       /* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+       mcu_timerio_input: pinctrl@40f04200 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x40f04200 0x00 0x28>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x0000000f>;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
+       /* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+       mcu_timerio_output: pinctrl@40f04280 {
+               compatible = "pinctrl-single";
+               reg = <0x00 0x40f04280 0x00 0x28>;
+               #pinctrl-cells = <1>;
+               pinctrl-single,register-width = <32>;
+               pinctrl-single,function-mask = <0x0000000f>;
+               /* Non-MPU Firmware usage */
+               status = "reserved";
+       };
+
        mcu_ram: sram@41c00000 {
                compatible = "mmio-sram";
                reg = <0x00 0x41c00000 0x00 0x100000>;