Initially when register shadowing was introduced (commit
3a0ab62f43de
("serial: imx: implement shadow registers for UCRx and UFCR")) the logic
to handle UCR2_SRST was wrong but documented consistently. Later the
handling was fixed, but the comment was not. This change makes up leeway
for the latter.
Fixes: 0aa821d846c0 ("serial: imx: fix cached UCR2 read on software reset")
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
/*
* UCR2_SRST is the only bit in the cached registers that might
* differ from the value that was last written. As it only
- * clears after being set, reread conditionally.
+ * automatically becomes one after being cleared, reread
+ * conditionally.
*/
if (!(sport->ucr2 & UCR2_SRST))
sport->ucr2 = readl(sport->port.membase + offset);