armv8/ls2085aqds: Add support of LS2085AQDS platform
authorYork Sun <yorksun@freescale.com>
Sat, 21 Mar 2015 02:28:23 +0000 (19:28 -0700)
committerYork Sun <yorksun@freescale.com>
Thu, 23 Apr 2015 15:55:58 +0000 (08:55 -0700)
The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
Signed-off-by: Bhupesh Sharma <bhupesh.sharma@freescale.com>
14 files changed:
arch/arm/Kconfig
arch/arm/cpu/armv8/fsl-lsch3/README
board/freescale/ls2085aqds/Kconfig [new file with mode: 0644]
board/freescale/ls2085aqds/MAINTAINERS [new file with mode: 0644]
board/freescale/ls2085aqds/Makefile [new file with mode: 0644]
board/freescale/ls2085aqds/README [new file with mode: 0644]
board/freescale/ls2085aqds/ddr.c [new file with mode: 0644]
board/freescale/ls2085aqds/ddr.h [new file with mode: 0644]
board/freescale/ls2085aqds/ls2085aqds.c [new file with mode: 0644]
board/freescale/ls2085aqds/ls2085aqds_qixis.h [new file with mode: 0644]
configs/ls2085aqds_defconfig [new file with mode: 0644]
include/configs/ls2085a_common.h
include/configs/ls2085aqds.h [new file with mode: 0644]
include/fsl_ddr_sdram.h

index 3702bb0..f8ef5dc 100644 (file)
@@ -711,6 +711,16 @@ config TARGET_LS2085A_SIMU
        select ARM64
        select ARMV8_MULTIENTRY
 
+config TARGET_LS2085AQDS
+       bool "Support ls2085aqds"
+       select ARM64
+       select ARMV8_MULTIENTRY
+       help
+         Support for Freescale LS2085AQDS platform
+         The LS2085A Development System (QDS) is a high-performance
+         development platform that supports the QorIQ LS2085A
+         Layerscape Architecture processor.
+
 config TARGET_LS1021AQDS
        bool "Support ls1021aqds"
        select CPU_V7
@@ -865,6 +875,7 @@ source "board/denx/m53evk/Kconfig"
 source "board/embest/mx6boards/Kconfig"
 source "board/esg/ima3-mx53/Kconfig"
 source "board/freescale/ls2085a/Kconfig"
+source "board/freescale/ls2085aqds/Kconfig"
 source "board/freescale/ls1021aqds/Kconfig"
 source "board/freescale/ls1021atwr/Kconfig"
 source "board/freescale/mx23evk/Kconfig"
index f781620..817ea1b 100644 (file)
@@ -11,28 +11,82 @@ for example LS2085A.
 
 Flash Layout
 ============
-A typical layout of various images (including Linux and other firmware images)
-is shown below considering a 32MB NOR flash device:
+
+(1) A typical layout of various images (including Linux and other firmware images)
+   is shown below considering a 32MB NOR flash device present on most
+   pre-silicon platforms (simulator and emulator):
 
        -------------------------
-       |       linux           |
+       |       FIT Image       |
+       | (linux + DTB + RFS)   |
        ------------------------- ----> 0x0120_0000
-       |       Debug Server    |
+       |       Debug Server FW |
        ------------------------- ----> 0x00C0_0000
-       |       AIOP SW         |
+       |       AIOP FW         |
        ------------------------- ----> 0x0070_0000
        |       MC FW           |
        ------------------------- ----> 0x006C_0000
-       | MC Data Path Layout   |
+       |       MC DPL Blob     |
        ------------------------- ----> 0x0020_0000
-       |       BootLoader      |
+       |       BootLoader + Env|
        ------------------------- ----> 0x0000_1000
        |       PBI             |
        ------------------------- ----> 0x0000_0080
        |       RCW             |
        ------------------------- ----> 0x0000_0000
 
-       32-MB NOR flash layout
+       32-MB NOR flash layout for pre-silicon platforms (simulator and emulator)
+
+(2) A typical layout of various images (including Linux and other firmware images)
+    is shown below considering a 128MB NOR flash device present on QDS
+    boards:
+       ----------------------------------------- ----> 0x5_8800_0000 ---
+       |       .. Unused .. (7M)               |                       |
+       ----------------------------------------- ----> 0x5_8790_0000   |
+       | FIT Image (linux + DTB + RFS) (40M)   |                       |
+       ----------------------------------------- ----> 0x5_8510_0000   |
+       |       PHY firmware (2M)               |                       |
+       ----------------------------------------- ----> 0x5_84F0_0000   | 64K
+       |       Debug Server FW (2M)            |                       | Alt
+       ----------------------------------------- ----> 0x5_84D0_0000   | Bank
+       |       AIOP FW (4M)                    |                       |
+       ----------------------------------------- ----> 0x5_8490_0000 (vbank4)
+       |       MC DPC Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8480_0000   |
+       |       MC DPL Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8470_0000   |
+       |       MC FW (4M)                      |                       |
+       ----------------------------------------- ----> 0x5_8430_0000   |
+       |       BootLoader Environment (1M)     |                       |
+       ----------------------------------------- ----> 0x5_8420_0000   |
+       |       BootLoader (1M)                 |                       |
+       ----------------------------------------- ----> 0x5_8410_0000   |
+       |       RCW and PBI (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8400_0000 ---
+       |       .. Unused .. (7M)               |                       |
+       ----------------------------------------- ----> 0x5_8390_0000   |
+       | FIT Image (linux + DTB + RFS) (40M)   |                       |
+       ----------------------------------------- ----> 0x5_8110_0000   |
+       |       PHY firmware (2M)               |                       |
+       ----------------------------------------- ----> 0x5_80F0_0000   | 64K
+       |       Debug Server FW (2M)            |                       | Bank
+       ----------------------------------------- ----> 0x5_80D0_0000   |
+       |       AIOP FW (4M)                    |                       |
+       ----------------------------------------- ----> 0x5_8090_0000 (vbank0)
+       |       MC DPC Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8080_0000   |
+       |       MC DPL Blob (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8070_0000   |
+       |       MC FW (4M)                      |                       |
+       ----------------------------------------- ----> 0x5_8030_0000   |
+       |       BootLoader Environment (1M)     |                       |
+       ----------------------------------------- ----> 0x5_8020_0000   |
+       |       BootLoader (1M)                 |                       |
+       ----------------------------------------- ----> 0x5_8010_0000   |
+       |       RCW and PBI (1M)                |                       |
+       ----------------------------------------- ----> 0x5_8000_0000 ---
+
+       128-MB NOR flash layout for QDS board
 
 Environment Variables
 =====================
diff --git a/board/freescale/ls2085aqds/Kconfig b/board/freescale/ls2085aqds/Kconfig
new file mode 100644 (file)
index 0000000..deb640d
--- /dev/null
@@ -0,0 +1,16 @@
+
+if TARGET_LS2085AQDS
+
+config SYS_BOARD
+       default "ls2085aqds"
+
+config SYS_VENDOR
+       default "freescale"
+
+config SYS_SOC
+       default "fsl-lsch3"
+
+config SYS_CONFIG_NAME
+       default "ls2085aqds"
+
+endif
diff --git a/board/freescale/ls2085aqds/MAINTAINERS b/board/freescale/ls2085aqds/MAINTAINERS
new file mode 100644 (file)
index 0000000..74b3721
--- /dev/null
@@ -0,0 +1,7 @@
+LS2085A BOARD
+M:     Prabhakar Kushwaha <prabhakar@freescale.com>
+S:     Maintained
+F:     board/freescale/ls2085aqds/
+F:     board/freescale/ls2085a/ls2085aqds.c
+F:     include/configs/ls2085aqds.h
+F:     configs/ls2085aqds_defconfig
diff --git a/board/freescale/ls2085aqds/Makefile b/board/freescale/ls2085aqds/Makefile
new file mode 100644 (file)
index 0000000..f174f33
--- /dev/null
@@ -0,0 +1,8 @@
+#
+# Copyright 2015 Freescale Semiconductor
+#
+# SPDX-License-Identifier:     GPL-2.0+
+#
+
+obj-y += ls2085aqds.o
+obj-y += ddr.o
diff --git a/board/freescale/ls2085aqds/README b/board/freescale/ls2085aqds/README
new file mode 100644 (file)
index 0000000..fb3938e
--- /dev/null
@@ -0,0 +1,129 @@
+Overview
+--------
+The LS2085A Development System (QDS) is a high-performance computing,
+evaluation, and development platform that supports the QorIQ LS2085A
+Layerscape Architecture processor. The LS2085AQDS provides validation and
+SW development platform for the Freescale LS2085A processor series, with
+a complete debugging environment.
+
+LS2085A SoC Overview
+------------------
+The LS2085A integrated multicore processor combines eight ARM Cortex-A57
+processor cores with high-performance data path acceleration logic and network
+and peripheral bus interfaces required for networking, telecom/datacom,
+wireless infrastructure, and mil/aerospace applications.
+
+The LS2085A SoC includes the following function and features:
+
+ - Eight 64-bit ARM Cortex-A57 CPUs
+ - 1 MB platform cache with ECC
+ - Two 64-bit DDR4 SDRAM memory controllers with ECC and interleaving support
+ - One secondary 32-bit DDR4 SDRAM memory controller, intended for use by
+  the AIOP
+ - Data path acceleration architecture (DPAA2) incorporating acceleration for
+ the following functions:
+   - Packet parsing, classification, and distribution (WRIOP)
+   - Queue and Hardware buffer management for scheduling, packet sequencing, and
+     congestion management, buffer allocation and de-allocation (QBMan)
+   - Cryptography acceleration (SEC) at up to 10 Gbps
+   - RegEx pattern matching acceleration (PME) at up to 10 Gbps
+   - Decompression/compression acceleration (DCE) at up to 20 Gbps
+   - Accelerated I/O processing (AIOP) at up to 20 Gbps
+   - QDMA engine
+ - 16 SerDes lanes at up to 10.3125 GHz
+ - Ethernet interfaces
+   - Up to eight 10 Gbps Ethernet MACs
+   - Up to eight 1 / 2.5 Gbps Ethernet MACs
+ - High-speed peripheral interfaces
+   - Four PCIe 3.0 controllers, one supporting SR-IOV
+ - Additional peripheral interfaces
+   - Two serial ATA (SATA 3.0) controllers
+   - Two high-speed USB 3.0 controllers with integrated PHY
+   - Enhanced secure digital host controller (eSDXC/eMMC)
+   - Serial peripheral interface (SPI) controller
+   - Quad Serial Peripheral Interface (QSPI) Controller
+   - Four I2C controllers
+   - Two DUARTs
+   - Integrated flash controller (IFC 2.0) supporting NAND and NOR flash
+ - Support for hardware virtualization and partitioning enforcement
+ - QorIQ platform's trust architecture 3.0
+ - Service processor (SP) provides pre-boot initialization and secure-boot
+  capabilities
+
+ LS2085AQDS board Overview
+ -----------------------
+ - SERDES Connections, 16 lanes supporting:
+      - PCI Express - 3.0
+      - SGMII, SGMII 2.5
+      - QSGMII
+      - SATA 3.0
+      - XAUI
+      - XFI
+ - DDR Controller
+     - Two ports of 72-bits (8-bits ECC) DDR4. Each port supports four
+       chip-selects and two DIMM connectors. Support is up to 2133MT/s.
+     - One port of 40-bits (8-bits ECC) DDR4 which supports four chip-selects
+       and two DIMM connectors. Support is up to 1600MT/s.
+ -IFC/Local Bus
+    - IFC rev. 2.0 implementation supporting Little Endian connection scheme.
+    - One in-socket 128 MB NOR flash 16-bit data bus
+    - One 512 MB NAND flash with ECC support
+    - IFC Test Port
+    - PromJet Port
+    - FPGA connection
+ - USB 3.0
+    - Two high speed USB 3.0 ports
+    - First USB 3.0 port configured as Host with Type-A connector
+    - Second USB 3.0 port configured as OTG with micro-AB connector
+ - SDHC: PCIe x1 Right Angle connector for supporting following cards
+    - 1/4-/8-bit SD/MMC Legacy CARD supporting 3.3V devices only
+    - 1-/4-/8-bit SD/MMC Card supporting 1.8V devices only
+    - 4-bit eMMC Card Rev 4.4 (1.8V only)
+    - 8-bit eMMC Card Rev 4.5 (1.8V only)
+    - SD Card Rev 2.0 and Rev 3.0
+ - DSPI: 3 high-speed flash Memory for storage
+    - 16 MB high-speed flash Memory for boot code and storage (up to 108MHz)
+    - 8 MB high-speed flash Memory (up to 104 MHz)
+    - 512 MB low-speed flash Memory (up to 40 MHz)
+ - QSPI: via NAND/QSPI Card
+ - 4 I2C controllers
+ - Two SATA onboard connectors
+ - UART
+   - Two 4-pin (HW control) or four 2-pin (SW control) serial ports at up to 115.2 Kbit/s
+   - Two DB9 D-Type connectors supporting one Serial port each
+ - ARM JTAG support
+
+Memory map from core's view
+----------------------------
+0x00_0000_0000 .. 0x00_000F_FFFF       Boot Rom
+0x00_0100_0000 .. 0x00_0FFF_FFFF       CCSR
+0x00_1800_0000 .. 0x00_181F_FFFF       OCRAM
+0x00_3000_0000 .. 0x00_3FFF_FFFF       IFC region #1
+0x00_8000_0000 .. 0x00_FFFF_FFFF       DDR region #1
+0x05_1000_0000 .. 0x05_FFFF_FFFF       IFC region #2
+0x80_8000_0000 .. 0xFF_FFFF_FFFF       DDR region #2
+
+Other addresses are either reserved, or not used directly by u-boot.
+This list should be updated when more addresses are used.
+
+IFC region map from core's view
+-------------------------------
+During boot i.e. IFC Region #1:-
+  0x30000000 - 0x37ffffff : 128MB : NOR flash
+  0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+  0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+
+After relocate to DDR i.e. IFC Region #2:-
+  0x5_1000_0000..0x5_1fff_ffff Memory Hole
+  0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
+  0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
+  0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
+  0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
+
+Booting Options
+---------------
+a) Promjet Boot
+b) NOR boot
+c) NAND boot
+d) SD boot
+e) QSPI boot
diff --git a/board/freescale/ls2085aqds/ddr.c b/board/freescale/ls2085aqds/ddr.c
new file mode 100644 (file)
index 0000000..6cd5e8b
--- /dev/null
@@ -0,0 +1,192 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#include <common.h>
+#include <fsl_ddr_sdram.h>
+#include <fsl_ddr_dimm_params.h>
+#include "ddr.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void fsl_ddr_board_options(memctl_options_t *popts,
+                               dimm_params_t *pdimm,
+                               unsigned int ctrl_num)
+{
+       u8 dq_mapping_0, dq_mapping_2, dq_mapping_3;
+       const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
+       ulong ddr_freq;
+       int slot;
+
+       if (ctrl_num > 2) {
+               printf("Not supported controller number %d\n", ctrl_num);
+               return;
+       }
+
+       for (slot = 0; slot < CONFIG_DIMM_SLOTS_PER_CTLR; slot++) {
+               if (pdimm[slot].n_ranks)
+                       break;
+       }
+
+       if (slot >= CONFIG_DIMM_SLOTS_PER_CTLR)
+               return;
+
+       /*
+        * we use identical timing for all slots. If needed, change the code
+        * to  pbsp = rdimms[ctrl_num] or pbsp = udimms[ctrl_num];
+        */
+       if (popts->registered_dimm_en)
+               pbsp = rdimms[ctrl_num];
+       else
+               pbsp = udimms[ctrl_num];
+
+
+       /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
+        * freqency and n_banks specified in board_specific_parameters table.
+        */
+       ddr_freq = get_ddr_freq(ctrl_num) / 1000000;
+       while (pbsp->datarate_mhz_high) {
+               if (pbsp->n_ranks == pdimm[slot].n_ranks &&
+                   (pdimm[slot].rank_density >> 30) >= pbsp->rank_gb) {
+                       if (ddr_freq <= pbsp->datarate_mhz_high) {
+                               popts->clk_adjust = pbsp->clk_adjust;
+                               popts->wrlvl_start = pbsp->wrlvl_start;
+                               popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+                               popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+                               goto found;
+                       }
+                       pbsp_highest = pbsp;
+               }
+               pbsp++;
+       }
+
+       if (pbsp_highest) {
+               printf("Error: board specific timing not found for data rate %lu MT/s\n"
+                       "Trying to use the highest speed (%u) parameters\n",
+                       ddr_freq, pbsp_highest->datarate_mhz_high);
+               popts->clk_adjust = pbsp_highest->clk_adjust;
+               popts->wrlvl_start = pbsp_highest->wrlvl_start;
+               popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
+               popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
+       } else {
+               panic("DIMM is not supported by this board");
+       }
+found:
+       debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n"
+               "\tclk_adjust %d, wrlvl_start %d, wrlvl_ctrl_2 0x%x, wrlvl_ctrl_3 0x%x\n",
+               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb,
+               pbsp->clk_adjust, pbsp->wrlvl_start, pbsp->wrlvl_ctl_2,
+               pbsp->wrlvl_ctl_3);
+
+       if (ctrl_num == CONFIG_DP_DDR_CTRL) {
+               /* force DDR bus width to 32 bits */
+               popts->data_bus_width = 1;
+               popts->otf_burst_chop_en = 0;
+               popts->burst_length = DDR_BL8;
+               popts->bstopre = 0;     /* enable auto precharge */
+               /*
+                * Layout optimization results byte mapping
+                * Byte 0 -> Byte ECC
+                * Byte 1 -> Byte 3
+                * Byte 2 -> Byte 2
+                * Byte 3 -> Byte 1
+                * Byte ECC -> Byte 0
+                */
+               dq_mapping_0 = pdimm[slot].dq_mapping[0];
+               dq_mapping_2 = pdimm[slot].dq_mapping[2];
+               dq_mapping_3 = pdimm[slot].dq_mapping[3];
+               pdimm[slot].dq_mapping[0] = pdimm[slot].dq_mapping[8];
+               pdimm[slot].dq_mapping[1] = pdimm[slot].dq_mapping[9];
+               pdimm[slot].dq_mapping[2] = pdimm[slot].dq_mapping[6];
+               pdimm[slot].dq_mapping[3] = pdimm[slot].dq_mapping[7];
+               pdimm[slot].dq_mapping[6] = dq_mapping_2;
+               pdimm[slot].dq_mapping[7] = dq_mapping_3;
+               pdimm[slot].dq_mapping[8] = dq_mapping_0;
+               pdimm[slot].dq_mapping[9] = 0;
+               pdimm[slot].dq_mapping[10] = 0;
+               pdimm[slot].dq_mapping[11] = 0;
+               pdimm[slot].dq_mapping[12] = 0;
+               pdimm[slot].dq_mapping[13] = 0;
+               pdimm[slot].dq_mapping[14] = 0;
+               pdimm[slot].dq_mapping[15] = 0;
+               pdimm[slot].dq_mapping[16] = 0;
+               pdimm[slot].dq_mapping[17] = 0;
+       }
+       /* To work at higher than 1333MT/s */
+       popts->half_strength_driver_enable = 0;
+       /*
+        * Write leveling override
+        */
+       popts->wrlvl_override = 1;
+       popts->wrlvl_sample = 0x0;      /* 32 clocks */
+
+       /*
+        * Rtt and Rtt_WR override
+        */
+       popts->rtt_override = 0;
+
+       /* Enable ZQ calibration */
+       popts->zq_en = 1;
+
+       if (ddr_freq < 2350) {
+               popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+                                 DDR_CDR1_ODT(DDR_CDR_ODT_60ohm);
+               popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_60ohm) |
+                                 DDR_CDR2_VREF_RANGE_2;
+       } else {
+               popts->ddr_cdr1 = DDR_CDR1_DHC_EN |
+                                 DDR_CDR1_ODT(DDR_CDR_ODT_100ohm);
+               popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_100ohm) |
+                                 DDR_CDR2_VREF_RANGE_2;
+       }
+}
+
+phys_size_t initdram(int board_type)
+{
+       phys_size_t dram_size;
+
+       puts("Initializing DDR....using SPD\n");
+
+       dram_size = fsl_ddr_sdram();
+
+       return dram_size;
+}
+
+void dram_init_banksize(void)
+{
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+       phys_size_t dp_ddr_size;
+#endif
+
+       gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
+       if (gd->ram_size > CONFIG_SYS_LS2_DDR_BLOCK1_SIZE) {
+               gd->bd->bi_dram[0].size = CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+               gd->bd->bi_dram[1].start = CONFIG_SYS_DDR_BLOCK2_BASE;
+               gd->bd->bi_dram[1].size = gd->ram_size -
+                                         CONFIG_SYS_LS2_DDR_BLOCK1_SIZE;
+       } else {
+               gd->bd->bi_dram[0].size = gd->ram_size;
+       }
+
+#ifdef CONFIG_SYS_DP_DDR_BASE_PHY
+       /* initialize DP-DDR here */
+       puts("DP-DDR:  ");
+       /*
+        * DDR controller use 0 as the base address for binding.
+        * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
+        */
+       dp_ddr_size = fsl_other_ddr_sdram(CONFIG_SYS_DP_DDR_BASE_PHY,
+                                         CONFIG_DP_DDR_CTRL,
+                                         CONFIG_DP_DDR_NUM_CTRLS,
+                                         CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR,
+                                         NULL, NULL, NULL);
+       if (dp_ddr_size) {
+               gd->bd->bi_dram[2].start = CONFIG_SYS_DP_DDR_BASE;
+               gd->bd->bi_dram[2].size = dp_ddr_size;
+       } else {
+               puts("Not detected");
+       }
+#endif
+}
diff --git a/board/freescale/ls2085aqds/ddr.h b/board/freescale/ls2085aqds/ddr.h
new file mode 100644 (file)
index 0000000..b76ea61
--- /dev/null
@@ -0,0 +1,92 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __DDR_H__
+#define __DDR_H__
+struct board_specific_parameters {
+       u32 n_ranks;
+       u32 datarate_mhz_high;
+       u32 rank_gb;
+       u32 clk_adjust;
+       u32 wrlvl_start;
+       u32 wrlvl_ctl_2;
+       u32 wrlvl_ctl_3;
+};
+
+/*
+ * These tables contain all valid speeds we want to override with board
+ * specific parameters. datarate_mhz_high values need to be in ascending order
+ * for each n_ranks group.
+ */
+
+static const struct board_specific_parameters udimm0[] = {
+       /*
+        * memory controller 0
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+        */
+       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
+       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2300, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters udimm2[] = {
+       /*
+        * memory controller 2
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+        */
+       {2,  1350, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
+       {2,  1666, 0, 4,   0xd, 0x0C0A0A00, 0x00000009,},
+       {2,  1900, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+       {2,  2200, 0, 4,   0xe, 0x0D0C0B00, 0x0000000A,},
+       {}
+};
+
+static const struct board_specific_parameters rdimm0[] = {
+       /*
+        * memory controller 0
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+        */
+       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 4,     7, 0x08090A0C, 0x0D0F100B,},
+       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {}
+};
+
+/* DP-DDR DIMM */
+static const struct board_specific_parameters rdimm2[] = {
+       /*
+        * memory controller 2
+        *   num|  hi| rank|  clk| wrlvl |   wrlvl   |  wrlvl
+        * ranks| mhz| GB  |adjst| start |   ctl2    |  ctl3
+        */
+       {2,  1350, 0, 4,     6, 0x0708090B, 0x0C0D0E09,},
+       {2,  1666, 0, 4,     7, 0x0B0A090C, 0x0D0F100B,},
+       {2,  1900, 0, 4,     7, 0x09090B0D, 0x0E10120B,},
+       {2,  2200, 0, 4,     8, 0x090A0C0F, 0x1012130C,},
+       {}
+};
+
+static const struct board_specific_parameters *udimms[] = {
+       udimm0,
+       udimm0,
+       udimm2,
+};
+
+static const struct board_specific_parameters *rdimms[] = {
+       rdimm0,
+       rdimm0,
+       rdimm2,
+};
+
+
+#endif
diff --git a/board/freescale/ls2085aqds/ls2085aqds.c b/board/freescale/ls2085aqds/ls2085aqds.c
new file mode 100644 (file)
index 0000000..f7ed5b9
--- /dev/null
@@ -0,0 +1,287 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+#include <common.h>
+#include <malloc.h>
+#include <errno.h>
+#include <netdev.h>
+#include <fsl_ifc.h>
+#include <fsl_ddr.h>
+#include <asm/io.h>
+#include <fdt_support.h>
+#include <libfdt.h>
+#include <fsl_debug_server.h>
+#include <fsl-mc/fsl_mc.h>
+#include <environment.h>
+#include <i2c.h>
+#include <asm/arch-fsl-lsch3/soc.h>
+
+#include "../common/qixis.h"
+#include "ls2085aqds_qixis.h"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+unsigned long long get_qixis_addr(void)
+{
+       unsigned long long addr;
+
+       if (gd->flags & GD_FLG_RELOC)
+               addr = QIXIS_BASE_PHYS;
+       else
+               addr = QIXIS_BASE_PHYS_EARLY;
+
+       /*
+        * IFC address under 256MB is mapped to 0x30000000, any address above
+        * is mapped to 0x5_10000000 up to 4GB.
+        */
+       addr = addr  > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
+
+       return addr;
+}
+
+int checkboard(void)
+{
+       char buf[64];
+       u8 sw;
+       static const char *const freq[] = {"100", "125", "156.25",
+                                           "100 separate SSCG"};
+       int clock;
+
+       sw = QIXIS_READ(arch);
+       printf("Board: %s, ", CONFIG_IDENT_STRING);
+       printf("Board Arch: V%d, ", sw >> 4);
+       printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
+
+       sw = QIXIS_READ(brdcfg[0]);
+       sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
+
+       if (sw < 0x8)
+               printf("vBank: %d\n", sw);
+       else if (sw == 0x8)
+               puts("PromJet\n");
+       else if (sw == 0x9)
+               puts("NAND\n");
+       else if (sw == 0x15)
+               printf("IFCCard\n");
+       else
+               printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
+
+       printf("FPGA: v%d (%s), build %d",
+              (int)QIXIS_READ(scver), qixis_read_tag(buf),
+              (int)qixis_read_minor());
+       /* the timestamp string contains "\n" at the end */
+       printf(" on %s", qixis_read_time(buf));
+
+       /*
+        * Display the actual SERDES reference clocks as configured by the
+        * dip switches on the board.  Note that the SWx registers could
+        * technically be set to force the reference clocks to match the
+        * values that the SERDES expects (or vice versa).  For now, however,
+        * we just display both values and hope the user notices when they
+        * don't match.
+        */
+       puts("SERDES1 Reference : ");
+       sw = QIXIS_READ(brdcfg[2]);
+       clock = (sw >> 6) & 3;
+       printf("Clock1 = %sMHz ", freq[clock]);
+       clock = (sw >> 4) & 3;
+       printf("Clock2 = %sMHz", freq[clock]);
+
+       puts("\nSERDES2 Reference : ");
+       clock = (sw >> 2) & 3;
+       printf("Clock1 = %sMHz ", freq[clock]);
+       clock = (sw >> 0) & 3;
+       printf("Clock2 = %sMHz\n", freq[clock]);
+
+       return 0;
+}
+
+unsigned long get_board_sys_clk(void)
+{
+       u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch (sysclk_conf & 0x0F) {
+       case QIXIS_SYSCLK_83:
+               return 83333333;
+       case QIXIS_SYSCLK_100:
+               return 100000000;
+       case QIXIS_SYSCLK_125:
+               return 125000000;
+       case QIXIS_SYSCLK_133:
+               return 133333333;
+       case QIXIS_SYSCLK_150:
+               return 150000000;
+       case QIXIS_SYSCLK_160:
+               return 160000000;
+       case QIXIS_SYSCLK_166:
+               return 166666666;
+       }
+       return 66666666;
+}
+
+unsigned long get_board_ddr_clk(void)
+{
+       u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
+
+       switch ((ddrclk_conf & 0x30) >> 4) {
+       case QIXIS_DDRCLK_100:
+               return 100000000;
+       case QIXIS_DDRCLK_125:
+               return 125000000;
+       case QIXIS_DDRCLK_133:
+               return 133333333;
+       }
+       return 66666666;
+}
+
+int select_i2c_ch_pca9547(u8 ch)
+{
+       int ret;
+
+       ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
+       if (ret) {
+               puts("PCA: failed to select proper channel\n");
+               return ret;
+       }
+
+       return 0;
+}
+
+int board_init(void)
+{
+       init_final_memctl_regs();
+
+#ifdef CONFIG_ENV_IS_NOWHERE
+       gd->env_addr = (ulong)&default_environment[0];
+#endif
+       select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
+
+       return 0;
+}
+
+int board_early_init_f(void)
+{
+       fsl_lsch3_early_init_f();
+       return 0;
+}
+
+void detail_board_ddr_info(void)
+{
+       puts("\nDDR    ");
+       print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
+       print_ddr_info(0);
+       if (gd->bd->bi_dram[2].size) {
+               puts("\nDP-DDR ");
+               print_size(gd->bd->bi_dram[2].size, "");
+               print_ddr_info(CONFIG_DP_DDR_CTRL);
+       }
+}
+
+int dram_init(void)
+{
+       gd->ram_size = initdram(0);
+
+       return 0;
+}
+
+#if defined(CONFIG_ARCH_MISC_INIT)
+int arch_misc_init(void)
+{
+#ifdef CONFIG_FSL_DEBUG_SERVER
+       debug_server_init();
+#endif
+
+       return 0;
+}
+#endif
+
+unsigned long get_dram_size_to_hide(void)
+{
+       unsigned long dram_to_hide = 0;
+
+/* Carve the Debug Server private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_DEBUG_SERVER
+       dram_to_hide += debug_server_get_dram_block_size();
+#endif
+
+/* Carve the MC private DRAM block from the end of DRAM */
+#ifdef CONFIG_FSL_MC_ENET
+       dram_to_hide += mc_get_dram_block_size();
+#endif
+
+       return dram_to_hide;
+}
+
+int board_eth_init(bd_t *bis)
+{
+       int error = 0;
+
+#ifdef CONFIG_FSL_MC_ENET
+       error = cpu_eth_init(bis);
+#endif
+
+       error = pci_eth_init(bis);
+
+       return error;
+}
+
+#ifdef CONFIG_FSL_MC_ENET
+void fdt_fixup_board_enet(void *fdt)
+{
+       int offset;
+
+       offset = fdt_path_offset(fdt, "/fsl-mc");
+
+       if (offset < 0)
+               offset = fdt_path_offset(fdt, "/fsl,dprc@0");
+
+       if (offset < 0) {
+               printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
+                      __func__, offset);
+               return;
+       }
+
+       if (get_mc_boot_status() == 0)
+               fdt_status_okay(fdt, offset);
+       else
+               fdt_status_fail(fdt, offset);
+}
+#endif
+
+#ifdef CONFIG_OF_BOARD_SETUP
+int ft_board_setup(void *blob, bd_t *bd)
+{
+       phys_addr_t base;
+       phys_size_t size;
+
+       ft_cpu_setup(blob, bd);
+
+       /* limit the memory size to bank 1 until Linux can handle 40-bit PA */
+       base = getenv_bootm_low();
+       size = getenv_bootm_size();
+       fdt_fixup_memory(blob, (u64)base, (u64)size);
+
+#ifdef CONFIG_FSL_MC_ENET
+       fdt_fixup_board_enet(blob);
+       fsl_mc_ldpaa_exit(bd);
+#endif
+
+       return 0;
+}
+#endif
+
+void qixis_dump_switch(void)
+{
+       int i, nr_of_cfgsw;
+
+       QIXIS_WRITE(cms[0], 0x00);
+       nr_of_cfgsw = QIXIS_READ(cms[1]);
+
+       puts("DIP switch settings dump:\n");
+       for (i = 1; i <= nr_of_cfgsw; i++) {
+               QIXIS_WRITE(cms[0], i);
+               printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
+       }
+}
diff --git a/board/freescale/ls2085aqds/ls2085aqds_qixis.h b/board/freescale/ls2085aqds/ls2085aqds_qixis.h
new file mode 100644 (file)
index 0000000..bb43e65
--- /dev/null
@@ -0,0 +1,26 @@
+/*
+ * Copyright 2015 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_QIXIS_H__
+#define __LS2_QDS_QIXIS_H__
+
+/* SYSCLK */
+#define QIXIS_SYSCLK_66                        0x0
+#define QIXIS_SYSCLK_83                        0x1
+#define QIXIS_SYSCLK_100               0x2
+#define QIXIS_SYSCLK_125               0x3
+#define QIXIS_SYSCLK_133               0x4
+#define QIXIS_SYSCLK_150               0x5
+#define QIXIS_SYSCLK_160               0x6
+#define QIXIS_SYSCLK_166               0x7
+
+/* DDRCLK */
+#define QIXIS_DDRCLK_66                        0x0
+#define QIXIS_DDRCLK_100               0x1
+#define QIXIS_DDRCLK_125               0x2
+#define QIXIS_DDRCLK_133               0x3
+
+#endif /*__LS2_QDS_QIXIS_H__*/
diff --git a/configs/ls2085aqds_defconfig b/configs/ls2085aqds_defconfig
new file mode 100644 (file)
index 0000000..e3a17a3
--- /dev/null
@@ -0,0 +1,3 @@
+CONFIG_SYS_EXTRA_OPTIONS="SYS_FSL_DDR4"
+CONFIG_ARM=y
+CONFIG_TARGET_LS2085AQDS=y
index 4b68106..29a86f6 100644 (file)
@@ -94,7 +94,7 @@
 #define CONFIG_SYS_I2C_MXC_I2C4                /* enable I2C bus 4 */
 
 /* Serial Port */
-#define CONFIG_CONS_INDEX       2
+#define CONFIG_CONS_INDEX       1
 #define CONFIG_SYS_NS16550
 #define CONFIG_SYS_NS16550_SERIAL
 #define CONFIG_SYS_NS16550_REG_SIZE     1
 #define CONFIG_FSL_IFC
 
 /*
- * During booting, CS0 needs to be at the region of 0x30000000, i.e. the IFC
- * address 0. But this region is limited to 256MB. To accommodate bigger NOR
- * flash and other devices, we will map CS0 to 0x580000000 after relocation.
+ * During booting, IFC is mapped at the region of 0x30000000.
+ * But this region is limited to 256MB. To accommodate NOR, promjet
+ * and FPGA. This region is divided as below:
+ * 0x30000000 - 0x37ffffff : 128MB : NOR flash
+ * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
+ * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
+ *
+ * To accommodate bigger NOR flash and other devices, we will map IFC
+ * chip selects to as below:
+ * 0x5_1000_0000..0x5_1fff_ffff        Memory Hole
+ * 0x5_2000_0000..0x5_3fff_ffff        IFC CSx (FPGA, NAND and others 512MB)
+ * 0x5_4000_0000..0x5_7fff_ffff        ASIC or others 1GB
+ * 0x5_8000_0000..0x5_bfff_ffff        IFC CS0 1GB (NOR/Promjet)
+ * 0x5_C000_0000..0x5_ffff_ffff        IFC CS1 1GB (NOR/Promjet)
+ *
+ * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
  * CONFIG_SYS_FLASH_BASE has the final address (core view)
  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
  */
+
 #define CONFIG_SYS_FLASH_BASE                  0x580000000ULL
 #define CONFIG_SYS_FLASH_BASE_PHYS             0x80000000
 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY       0x00000000
 
+#define CONFIG_SYS_FLASH1_BASE_PHYS            0xC0000000
+#define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY      0x8000000
+
 #ifndef CONFIG_SYS_NO_FLASH
 #define CONFIG_FLASH_CFI_DRIVER
 #define CONFIG_SYS_FLASH_CFI
 #define CONFIG_SYS_FLASH_QUIET_TEST
 #endif
 
-#define CONFIG_SYS_NAND_BASE           0x520000000
-#define CONFIG_SYS_NAND_BASE_PHYS      0x20000000
+#ifndef __ASSEMBLY__
+unsigned long long get_qixis_addr(void);
+#endif
+#define QIXIS_BASE                             get_qixis_addr()
+#define QIXIS_BASE_PHYS                                0x20000000
+#define QIXIS_BASE_PHYS_EARLY                  0xC000000
+
+#define CONFIG_SYS_NAND_BASE                   0x530000000ULL
+#define CONFIG_SYS_NAND_BASE_PHYS              0x30000000
 
 /* Debug Server firmware */
 #define CONFIG_SYS_DEBUG_SERVER_DRAM_BLOCK_MIN_SIZE    (512UL * 1024 * 1024)
                                "hugepages=16"
 #define CONFIG_BOOTCOMMAND             "cp.b $kernel_start $kernel_load "     \
                                        "$kernel_size && bootm $kernel_load"
-#define CONFIG_BOOTDELAY               1
+#define CONFIG_BOOTDELAY               10
 
 /* Monitor Command Prompt */
 #define CONFIG_SYS_CBSIZE              512     /* Console I/O Buffer Size */
diff --git a/include/configs/ls2085aqds.h b/include/configs/ls2085aqds.h
new file mode 100644 (file)
index 0000000..b1d2d48
--- /dev/null
@@ -0,0 +1,283 @@
+/*
+ * Copyright 2015 Freescale Semiconductor
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ */
+
+#ifndef __LS2_QDS_H
+#define __LS2_QDS_H
+
+#include "ls2085a_common.h"
+#include <config_cmd_default.h>
+
+#define CONFIG_IDENT_STRING            " LS2085A-QDS"
+#define CONFIG_BOOTP_VCI_STRING                "U-boot.LS2085A-QDS"
+
+#define CONFIG_DISPLAY_BOARDINFO
+
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+unsigned long get_board_ddr_clk(void);
+#endif
+
+#define CONFIG_SYS_CLK_FREQ            get_board_sys_clk()
+#define CONFIG_DDR_CLK_FREQ            get_board_ddr_clk()
+#define COUNTER_FREQUENCY_REAL         (CONFIG_SYS_CLK_FREQ/4)
+
+#define CONFIG_DDR_SPD
+#define CONFIG_DDR_ECC
+#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
+#define CONFIG_MEM_INIT_VALUE          0xdeadbeef
+#define SPD_EEPROM_ADDRESS1    0x51
+#define SPD_EEPROM_ADDRESS2    0x52
+#define SPD_EEPROM_ADDRESS3    0x53
+#define SPD_EEPROM_ADDRESS4    0x54
+#define SPD_EEPROM_ADDRESS5    0x55
+#define SPD_EEPROM_ADDRESS6    0x56    /* dummy address */
+#define SPD_EEPROM_ADDRESS     SPD_EEPROM_ADDRESS1
+#define CONFIG_SYS_SPD_BUS_NUM 0       /* SPD on I2C bus 0 */
+#define CONFIG_DIMM_SLOTS_PER_CTLR             2
+#define CONFIG_CHIP_SELECTS_PER_CTRL           4
+#define CONFIG_DP_DDR_DIMM_SLOTS_PER_CTLR      1
+#define CONFIG_FSL_DDR_BIST    /* enable built-in memory test */
+
+/* undefined CONFIG_FSL_DDR_SYNC_REFRESH for simulator */
+
+#define CONFIG_SYS_NOR0_CSPR_EXT       (0x0)
+#define CONFIG_SYS_NOR_AMASK           IFC_AMASK(128*1024*1024)
+#define CONFIG_SYS_NOR_AMASK_EARLY     IFC_AMASK(64*1024*1024)
+
+#define CONFIG_SYS_NOR0_CSPR                                   \
+       (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS)             | \
+       CSPR_PORT_SIZE_16                                       | \
+       CSPR_MSEL_NOR                                           | \
+       CSPR_V)
+#define CONFIG_SYS_NOR0_CSPR_EARLY                             \
+       (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS_EARLY)       | \
+       CSPR_PORT_SIZE_16                                       | \
+       CSPR_MSEL_NOR                                           | \
+       CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR                                   \
+       (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS)            | \
+       CSPR_PORT_SIZE_16                                       | \
+       CSPR_MSEL_NOR                                           | \
+       CSPR_V)
+#define CONFIG_SYS_NOR1_CSPR_EARLY                             \
+       (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH1_BASE_PHYS_EARLY)      | \
+       CSPR_PORT_SIZE_16                                       | \
+       CSPR_MSEL_NOR                                           | \
+       CSPR_V)
+#define CONFIG_SYS_NOR_CSOR    CSOR_NOR_ADM_SHIFT(12)
+#define CONFIG_SYS_NOR_FTIM0   (FTIM0_NOR_TACSE(0x4) | \
+                               FTIM0_NOR_TEADC(0x5) | \
+                               FTIM0_NOR_TEAHC(0x5))
+#define CONFIG_SYS_NOR_FTIM1   (FTIM1_NOR_TACO(0x35) | \
+                               FTIM1_NOR_TRAD_NOR(0x1a) |\
+                               FTIM1_NOR_TSEQRAD_NOR(0x13))
+#define CONFIG_SYS_NOR_FTIM2   (FTIM2_NOR_TCS(0x4) | \
+                               FTIM2_NOR_TCH(0x4) | \
+                               FTIM2_NOR_TWPH(0x0E) | \
+                               FTIM2_NOR_TWP(0x1c))
+#define CONFIG_SYS_NOR_FTIM3   0x04000000
+#define CONFIG_SYS_IFC_CCR     0x01000000
+
+#ifndef CONFIG_SYS_NO_FLASH
+#define CONFIG_FLASH_CFI_DRIVER
+#define CONFIG_SYS_FLASH_CFI
+#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
+#define CONFIG_SYS_FLASH_QUIET_TEST
+#define CONFIG_FLASH_SHOW_PROGRESS     45 /* count down from 45/5: 9..1 */
+
+#define CONFIG_SYS_MAX_FLASH_BANKS     2       /* number of banks */
+#define CONFIG_SYS_MAX_FLASH_SECT      1024    /* sectors per device */
+#define CONFIG_SYS_FLASH_ERASE_TOUT    60000   /* Flash Erase Timeout (ms) */
+#define CONFIG_SYS_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (ms) */
+
+#define CONFIG_SYS_FLASH_EMPTY_INFO
+#define CONFIG_SYS_FLASH_BANKS_LIST    { CONFIG_SYS_FLASH_BASE,\
+                                        CONFIG_SYS_FLASH_BASE + 0x40000000}
+#endif
+
+#define CONFIG_NAND_FSL_IFC
+#define CONFIG_SYS_NAND_MAX_ECCPOS     256
+#define CONFIG_SYS_NAND_MAX_OOBFREE    2
+
+
+#define CONFIG_SYS_NAND_CSPR_EXT       (0x0)
+#define CONFIG_SYS_NAND_CSPR   (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
+                               | CSPR_MSEL_NAND        /* MSEL = NAND */ \
+                               | CSPR_V)
+#define CONFIG_SYS_NAND_AMASK  IFC_AMASK(64 * 1024)
+
+#define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
+                               | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
+                               | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
+                               | CSOR_NAND_RAL_3       /* RAL = 3Byes */ \
+                               | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
+                               | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
+                               | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
+
+#define CONFIG_SYS_NAND_ONFI_DETECTION
+
+/* ONFI NAND Flash mode0 Timing Params */
+#define CONFIG_SYS_NAND_FTIM0          (FTIM0_NAND_TCCST(0x07) | \
+                                       FTIM0_NAND_TWP(0x18)   | \
+                                       FTIM0_NAND_TWCHT(0x07) | \
+                                       FTIM0_NAND_TWH(0x0a))
+#define CONFIG_SYS_NAND_FTIM1          (FTIM1_NAND_TADLE(0x32) | \
+                                       FTIM1_NAND_TWBE(0x39)  | \
+                                       FTIM1_NAND_TRR(0x0e)   | \
+                                       FTIM1_NAND_TRP(0x18))
+#define CONFIG_SYS_NAND_FTIM2          (FTIM2_NAND_TRAD(0x0f) | \
+                                       FTIM2_NAND_TREH(0x0a) | \
+                                       FTIM2_NAND_TWHRE(0x1e))
+#define CONFIG_SYS_NAND_FTIM3          0x0
+
+#define CONFIG_SYS_NAND_BASE_LIST      { CONFIG_SYS_NAND_BASE }
+#define CONFIG_SYS_MAX_NAND_DEVICE     1
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_CMD_NAND
+
+#define CONFIG_SYS_NAND_BLOCK_SIZE     (128 * 1024)
+
+#define CONFIG_FSL_QIXIS       /* use common QIXIS code */
+#define QIXIS_LBMAP_SWITCH             0x06
+#define QIXIS_LBMAP_MASK               0x0f
+#define QIXIS_LBMAP_SHIFT              0
+#define QIXIS_LBMAP_DFLTBANK           0x00
+#define QIXIS_LBMAP_ALTBANK            0x04
+#define QIXIS_RST_CTL_RESET            0x31
+#define QIXIS_RCFG_CTL_RECONFIG_IDLE   0x20
+#define QIXIS_RCFG_CTL_RECONFIG_START  0x21
+#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
+#define        QIXIS_RST_FORCE_MEM             0x01
+
+#define CONFIG_SYS_CSPR3_EXT   (0x0)
+#define CONFIG_SYS_CSPR3       (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS_EARLY) \
+                               | CSPR_PORT_SIZE_8 \
+                               | CSPR_MSEL_GPCM \
+                               | CSPR_V)
+#define CONFIG_SYS_CSPR3_FINAL (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
+                               | CSPR_PORT_SIZE_8 \
+                               | CSPR_MSEL_GPCM \
+                               | CSPR_V)
+
+#define CONFIG_SYS_AMASK3      IFC_AMASK(64*1024)
+#define CONFIG_SYS_CSOR3       CSOR_GPCM_ADM_SHIFT(12)
+/* QIXIS Timing parameters for IFC CS3 */
+#define CONFIG_SYS_CS3_FTIM0           (FTIM0_GPCM_TACSE(0x0e) | \
+                                       FTIM0_GPCM_TEADC(0x0e) | \
+                                       FTIM0_GPCM_TEAHC(0x0e))
+#define CONFIG_SYS_CS3_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
+                                       FTIM1_GPCM_TRAD(0x3f))
+#define CONFIG_SYS_CS3_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
+                                       FTIM2_GPCM_TCH(0xf) | \
+                                       FTIM2_GPCM_TWP(0x3E))
+#define CONFIG_SYS_CS3_FTIM3           0x0
+
+#define CONFIG_SYS_CSPR0_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR0               CONFIG_SYS_NOR0_CSPR_EARLY
+#define CONFIG_SYS_CSPR0_FINAL         CONFIG_SYS_NOR0_CSPR
+#define CONFIG_SYS_AMASK0              CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR0               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS0_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS0_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS0_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS0_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR1_EXT           CONFIG_SYS_NOR0_CSPR_EXT
+#define CONFIG_SYS_CSPR1               CONFIG_SYS_NOR1_CSPR_EARLY
+#define CONFIG_SYS_CSPR1_FINAL         CONFIG_SYS_NOR1_CSPR
+#define CONFIG_SYS_AMASK1              CONFIG_SYS_NOR_AMASK_EARLY
+#define CONFIG_SYS_AMASK1_FINAL                CONFIG_SYS_NOR_AMASK
+#define CONFIG_SYS_CSOR1               CONFIG_SYS_NOR_CSOR
+#define CONFIG_SYS_CS1_FTIM0           CONFIG_SYS_NOR_FTIM0
+#define CONFIG_SYS_CS1_FTIM1           CONFIG_SYS_NOR_FTIM1
+#define CONFIG_SYS_CS1_FTIM2           CONFIG_SYS_NOR_FTIM2
+#define CONFIG_SYS_CS1_FTIM3           CONFIG_SYS_NOR_FTIM3
+#define CONFIG_SYS_CSPR2_EXT           CONFIG_SYS_NAND_CSPR_EXT
+#define CONFIG_SYS_CSPR2               CONFIG_SYS_NAND_CSPR
+#define CONFIG_SYS_AMASK2              CONFIG_SYS_NAND_AMASK
+#define CONFIG_SYS_CSOR2               CONFIG_SYS_NAND_CSOR
+#define CONFIG_SYS_CS2_FTIM0           CONFIG_SYS_NAND_FTIM0
+#define CONFIG_SYS_CS2_FTIM1           CONFIG_SYS_NAND_FTIM1
+#define CONFIG_SYS_CS2_FTIM2           CONFIG_SYS_NAND_FTIM2
+#define CONFIG_SYS_CS2_FTIM3           CONFIG_SYS_NAND_FTIM3
+
+/* Debug Server firmware */
+#define CONFIG_SYS_DEBUG_SERVER_FW_IN_NOR
+#define CONFIG_SYS_DEBUG_SERVER_FW_ADDR        0x580D00000ULL
+
+/* MC firmware */
+#define CONFIG_SYS_LS_MC_FW_IN_NOR
+#define CONFIG_SYS_LS_MC_FW_ADDR       0x580300000ULL
+
+#define CONFIG_SYS_LS_MC_DPL_IN_NOR
+#define CONFIG_SYS_LS_MC_DPL_ADDR      0x580700000ULL
+
+#define CONFIG_SYS_LS_MC_DPC_IN_NOR
+#define CONFIG_SYS_LS_MC_DPC_ADDR      0x580800000ULL
+
+#define CONFIG_SYS_LS_MC_BOOT_TIMEOUT_MS 5000
+
+/*
+ * I2C
+ */
+#define I2C_MUX_PCA_ADDR               0x77
+#define I2C_MUX_PCA_ADDR_PRI           0x77 /* Primary Mux*/
+
+/* I2C bus multiplexer */
+#define I2C_MUX_CH_DEFAULT      0x8
+
+/*
+ * RTC configuration
+ */
+#define RTC
+#define CONFIG_RTC_DS3231               1
+#define CONFIG_SYS_I2C_RTC_ADDR         0x68
+
+/* EEPROM */
+#define CONFIG_ID_EEPROM
+#define CONFIG_CMD_EEPROM
+#define CONFIG_SYS_I2C_EEPROM_NXID
+#define CONFIG_SYS_EEPROM_BUS_NUM      0
+#define CONFIG_SYS_I2C_EEPROM_ADDR     0x57
+#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
+#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+
+#define CONFIG_ENV_IS_IN_FLASH
+#define CONFIG_ENV_ADDR                        (CONFIG_SYS_FLASH_BASE + 0x200000)
+#define CONFIG_ENV_SECT_SIZE           0x20000
+#define CONFIG_ENV_SIZE                        0x2000
+
+#define CONFIG_FSL_MEMAC
+#define CONFIG_PCI             /* Enable PCIE */
+#define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
+
+#ifdef CONFIG_PCI
+#define CONFIG_NET_MULTI
+#define CONFIG_PCI_PNP
+#define CONFIG_E1000
+#define CONFIG_PCI_SCAN_SHOW
+#define CONFIG_CMD_PCI
+#define CONFIG_CMD_NET
+#endif
+
+
+
+/* Initial environment variables */
+#undef CONFIG_EXTRA_ENV_SETTINGS
+#define CONFIG_EXTRA_ENV_SETTINGS              \
+       "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
+       "loadaddr=0x80100000\0"                 \
+       "kernel_addr=0x100000\0"                \
+       "ramdisk_addr=0x800000\0"               \
+       "ramdisk_size=0x2000000\0"              \
+       "fdt_high=0xa0000000\0"                 \
+       "initrd_high=0xffffffffffffffff\0"      \
+       "kernel_start=0x581100000\0"            \
+       "kernel_load=0xa0000000\0"              \
+       "kernel_size=0x1000000\0"
+
+#endif /* __LS2_QDS_H */
index 6358b6f..e5b6e03 100644 (file)
@@ -167,6 +167,7 @@ typedef struct ddr4_spd_eeprom_s generic_spd_eeprom_t;
 #define DDR_CDR2_ODT(x) (x & DDR_CDR2_ODT_MASK)
 #define DDR_CDR2_VREF_OVRD(x)  (0x00008080 | ((((x) - 37) & 0x3F) << 8))
 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
+#define DDR_CDR2_VREF_RANGE_2  0x00000040
 
 #if (defined(CONFIG_SYS_FSL_DDR_VER) && \
        (CONFIG_SYS_FSL_DDR_VER >= FSL_DDR_VER_4_7))