Patch by Tom Guilliams, 20 Jun 2003:

added CONFIG_750FX support for IBM 750FX processors

diff --git a/CHANGELOG b/CHANGELOG
index 9364c95..fc06773 100644 (file)
--- a/CHANGELOG
+++ b/CHANGELOG
@@ -2,6 +2,9 @@
 Changes since U-Boot 0.3.1:
 ======================================================================
 
+* Patch by Tom Guilliams, 20 Jun 2003:
+  added CONFIG_750FX support for IBM 750FX processors
+
 * Patch by Devin Crumb, 02 Apr 2003:
   Fix clock divider rounding problem in drivers/serial.c
 

diff --git a/README b/README
index 31fc373..e33c601 100644 (file)
--- a/README
+++ b/README
@@ -301,6 +301,7 @@ The following options need to be configured:
        or      CONFIG_405GP
        or      CONFIG_440
        or      CONFIG_MPC74xx
+       or      CONFIG_750FX
 
                ARM based CPUs:
                ---------------

diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c
index c265ce2..19f8ff8 100644 (file)
--- a/cpu/74xx_7xx/cpu.c
+++ b/cpu/74xx_7xx/cpu.c
@@ -64,7 +64,7 @@ get_cpu_type(void)
        case 0x0008:
                type = CPU_750;
 
-                if (((pvr >> 8) & 0xff) == 0x01) {
+               if (((pvr >> 8) & 0xff) == 0x01) {
                        type = CPU_750CX;       /* old CX (80100 and 8010x?)*/
                } else if (((pvr >> 8) & 0xff) == 0x22) {
                        type = CPU_750CX;       /* CX (82201,82202) and CXe (82214) */
@@ -72,14 +72,18 @@ get_cpu_type(void)
                        type = CPU_750CX;       /* CXe (83311) */
                } else if (((pvr >> 12) & 0xF) == 0x3) {
                        type = CPU_755;
-                }
+               }
+               break;
+
+       case 0x7000:
+               type = CPU_750FX;
                break;
 
        case 0x800C:
                type = CPU_7410;
                break;
 
-        case 0x8000:
+       case 0x8000:
                type = CPU_7450;
                break;
 
@@ -116,6 +120,10 @@ int checkcpu (void)
                str = "750";
                break;
 
+       case CPU_750FX:
+               str = "750FX";
+               break;
+
        case CPU_755:
                str = "755";
                break;
@@ -124,16 +132,16 @@ int checkcpu (void)
                str = "MPC7400";
                break;
 
-        case CPU_7410:
-                str = "MPC7410";
+       case CPU_7410:
+               str = "MPC7410";
                break;
 
-        case CPU_7450:
-                str = "MPC7450";
+       case CPU_7450:
+               str = "MPC7450";
                break;
 
        default:
-                printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
+               printf("Unknown CPU -- PVR: 0x%08x\n", pvr);
                return -1;
        }
 
@@ -146,8 +154,8 @@ PR_CLK:
 #endif
 /* these two functions are unimplemented currently [josh] */
 
-/* ------------------------------------------------------------------------- */
-/* L1 i-cache                                                                */
+/* -------------------------------------------------------------------- */
+/* L1 i-cache                                                          */
 
 int
 checkicache(void)
@@ -155,8 +163,8 @@ checkicache(void)
        return 0; /* XXX */
 }
 
-/* ------------------------------------------------------------------------- */
-/* L1 d-cache                                                                */
+/* -------------------------------------------------------------------- */
+/* L1 d-cache                                                          */
 
 int
 checkdcache(void)
@@ -164,7 +172,7 @@ checkdcache(void)
        return 0; /* XXX */
 }
 
-/* ------------------------------------------------------------------------- */
+/* -------------------------------------------------------------------- */
 
 static inline void
 soft_restart(unsigned long addr)

diff --git a/cpu/74xx_7xx/speed.c b/cpu/74xx_7xx/speed.c
index ac99bcd..23b71d4 100644 (file)
--- a/cpu/74xx_7xx/speed.c
+++ b/cpu/74xx_7xx/speed.c
@@ -48,6 +48,33 @@ static const int hid1_multipliers_x_10[] = {
        0       /* 1111 - off */
 };
 
+static const int hid1_fx_multipliers_x_10[] = {
+        00,     /* 0000 - off */
+        00,     /* 0001 - off */
+        10,     /* 0010 - bypass */
+        10,     /* 0011 - bypass */
+        20,     /* 0100 - 2x */
+        25,     /* 0101 - 2.5x */
+        30,     /* 0110 - 3x */
+        35,     /* 0111 - 3.5x */
+        40,     /* 1000 - 4x */
+        45,     /* 1001 - 4.5x */
+        50,     /* 1010 - 5x */
+        55,     /* 1011 - 5.5x */
+        60,     /* 1100 - 6x */
+        65,     /* 1101 - 6.5x */
+        70,     /* 1110 - 7x */
+        75,     /* 1111 - 7.5 */
+        80,     /* 10000 - 8x */
+        85,     /* 10001 - 8.5x */
+        90,     /* 10010 - 9x */
+        95,     /* 10011 - 9.5x */
+        100,    /* 10100 - 10x */
+        110,    /* 10101 - 11x */
+        120,    /* 10110 - 12x */
+};
+
+
 /* ------------------------------------------------------------------------- */
 
 /*
@@ -59,9 +86,13 @@ static const int hid1_multipliers_x_10[] = {
 int get_clocks (void)
 {
        DECLARE_GLOBAL_DATA_PTR;
-
+#ifdef CONFIG_750FX
+        ulong clock = CFG_BUS_CLK * \
+                      hid1_fx_multipliers_x_10[get_hid1 () >> 27] / 10;
+#else
        ulong clock = CFG_BUS_CLK * \
                      hid1_multipliers_x_10[get_hid1 () >> 28] / 10;
+#endif
        gd->cpu_clk = clock;
        gd->bus_clk = CFG_BUS_CLK;
 

diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S
index a37f924..4857908 100644 (file)
--- a/cpu/74xx_7xx/start.S
+++ b/cpu/74xx_7xx/start.S
@@ -379,11 +379,23 @@ invalidate_bats:
        mtspr   IBAT1U, r0
        mtspr   IBAT2U, r0
        mtspr   IBAT3U, r0
+#ifdef CONFIG_750FX
+       mtspr   IBAT4U, r0
+       mtspr   IBAT5U, r0
+       mtspr   IBAT6U, r0
+       mtspr   IBAT7U, r0
+#endif
        isync
        mtspr   DBAT0U, r0
        mtspr   DBAT1U, r0
        mtspr   DBAT2U, r0
        mtspr   DBAT3U, r0
+#ifdef CONFIG_750FX
+        mtspr   DBAT4U, r0
+        mtspr   DBAT5U, r0
+        mtspr   DBAT6U, r0
+        mtspr   DBAT7U, r0
+#endif
        isync
        sync
        blr
@@ -465,6 +477,80 @@ setup_bats:
        mtspr   DBAT3U, r3
        isync
 
+#ifdef CONFIG_750FX
+       /* IBAT 4 */
+        addis   r4, r0, CFG_IBAT4L@h
+        ori     r4, r4, CFG_IBAT4L@l
+        addis   r3, r0, CFG_IBAT4U@h
+        ori     r3, r3, CFG_IBAT4U@l
+        mtspr   IBAT4L, r4
+        mtspr   IBAT4U, r3
+        isync
+
+       /* DBAT 4 */
+        addis   r4, r0, CFG_DBAT4L@h
+        ori     r4, r4, CFG_DBAT4L@l
+        addis   r3, r0, CFG_DBAT4U@h
+        ori     r3, r3, CFG_DBAT4U@l
+        mtspr   DBAT4L, r4
+        mtspr   DBAT4U, r3
+        isync
+
+        /* IBAT 5 */
+        addis   r4, r0, CFG_IBAT5L@h
+        ori     r4, r4, CFG_IBAT5L@l
+        addis   r3, r0, CFG_IBAT5U@h
+        ori     r3, r3, CFG_IBAT5U@l
+        mtspr   IBAT5L, r4
+        mtspr   IBAT5U, r3
+        isync
+
+       /* DBAT 5 */
+        addis   r4, r0, CFG_DBAT5L@h
+        ori     r4, r4, CFG_DBAT5L@l
+        addis   r3, r0, CFG_DBAT5U@h
+        ori     r3, r3, CFG_DBAT5U@l
+        mtspr   DBAT5L, r4
+        mtspr   DBAT5U, r3
+        isync
+
+        /* IBAT 6 */
+        addis   r4, r0, CFG_IBAT6L@h
+        ori     r4, r4, CFG_IBAT6L@l
+        addis   r3, r0, CFG_IBAT6U@h
+        ori     r3, r3, CFG_IBAT6U@l
+        mtspr   IBAT6L, r4
+        mtspr   IBAT6U, r3
+        isync
+
+       /* DBAT 6 */
+        addis   r4, r0, CFG_DBAT6L@h
+        ori     r4, r4, CFG_DBAT6L@l
+        addis   r3, r0, CFG_DBAT6U@h
+        ori     r3, r3, CFG_DBAT6U@l
+        mtspr   DBAT6L, r4
+        mtspr   DBAT6U, r3
+        isync
+
+        /* IBAT 7 */
+        addis   r4, r0, CFG_IBAT7L@h
+        ori     r4, r4, CFG_IBAT7L@l
+        addis   r3, r0, CFG_IBAT7U@h
+        ori     r3, r3, CFG_IBAT7U@l
+        mtspr   IBAT7L, r4
+        mtspr   IBAT7U, r3
+        isync
+
+       /* DBAT 7 */
+        addis   r4, r0, CFG_DBAT7L@h
+        ori     r4, r4, CFG_DBAT7L@l
+        addis   r3, r0, CFG_DBAT7U@h
+        ori     r3, r3, CFG_DBAT7U@l
+        mtspr   DBAT7L, r4
+        mtspr   DBAT7U, r3
+        isync
+#endif
+
        /* bats are done, now invalidate the TLBs */
 
        addis   r3, 0, 0x0000

diff --git a/include/74xx_7xx.h b/include/74xx_7xx.h
index 193ba6c..03cbeff 100644 (file)
--- a/include/74xx_7xx.h
+++ b/include/74xx_7xx.h
@@ -108,7 +108,7 @@ typedef enum __cpu_t {
        CPU_740, CPU_750,
        CPU_740P, CPU_750P,
        CPU_745, CPU_755,
-       CPU_750CX,
+       CPU_750CX, CPU_750FX,
        CPU_7400,
        CPU_7410,
        CPU_7450,

diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h
index 9c88b49..8835139 100644 (file)
--- a/include/asm-ppc/processor.h
+++ b/include/asm-ppc/processor.h
@@ -95,6 +95,14 @@
 #define        SPRN_DBAT2U     0x21C   /* Data BAT 2 Upper Register */
 #define        SPRN_DBAT3L     0x21F   /* Data BAT 3 Lower Register */
 #define        SPRN_DBAT3U     0x21E   /* Data BAT 3 Upper Register */
+#define        SPRN_DBAT4L     0x238   /* Data BAT 4 Lower Register */
+#define        SPRN_DBAT4U     0x239   /* Data BAT 4 Upper Register */
+#define        SPRN_DBAT5L     0x23A   /* Data BAT 5 Lower Register */
+#define        SPRN_DBAT5U     0x23B   /* Data BAT 5 Upper Register */
+#define        SPRN_DBAT6L     0x23C   /* Data BAT 6 Lower Register */
+#define        SPRN_DBAT6U     0x23D   /* Data BAT 6 Upper Register */
+#define        SPRN_DBAT7L     0x23E   /* Data BAT 7 Lower Register */
+#define        SPRN_DBAT7U     0x23F   /* Data BAT 7 Lower Register */
 #define        SPRN_DBCR       0x3F2   /* Debug Control Regsiter */
 #define          DBCR_EDM      0x80000000
 #define          DBCR_IDM      0x40000000
@@ -195,6 +203,14 @@
 #define        SPRN_IBAT2U     0x214   /* Instruction BAT 2 Upper Register */
 #define        SPRN_IBAT3L     0x217   /* Instruction BAT 3 Lower Register */
 #define        SPRN_IBAT3U     0x216   /* Instruction BAT 3 Upper Register */
+#define        SPRN_IBAT4L     0x230   /* Instruction BAT 4 Lower Register */
+#define        SPRN_IBAT4U     0x231   /* Instruction BAT 4 Upper Register */
+#define        SPRN_IBAT5L     0x232   /* Instruction BAT 5 Lower Register */
+#define        SPRN_IBAT5U     0x233   /* Instruction BAT 5 Upper Register */
+#define        SPRN_IBAT6L     0x234   /* Instruction BAT 6 Lower Register */
+#define        SPRN_IBAT6U     0x235   /* Instruction BAT 6 Upper Register */
+#define        SPRN_IBAT7L     0x236   /* Instruction BAT 7 Lower Register */
+#define        SPRN_IBAT7U     0x237   /* Instruction BAT 7 Lower Register */
 #define        SPRN_ICCR       0x3FB   /* Instruction Cache Cacheability Register */
 #define          ICCR_NOCACHE          0       /* Noncacheable */
 #define          ICCR_CACHE            1       /* Cacheable */
@@ -305,6 +321,14 @@
 #define        DBAT2U  SPRN_DBAT2U     /* Data BAT 2 Upper Register */
 #define        DBAT3L  SPRN_DBAT3L     /* Data BAT 3 Lower Register */
 #define        DBAT3U  SPRN_DBAT3U     /* Data BAT 3 Upper Register */
+#define        DBAT4L  SPRN_DBAT4L     /* Data BAT 4 Lower Register */
+#define        DBAT4U  SPRN_DBAT4U     /* Data BAT 4 Upper Register */
+#define        DBAT5L  SPRN_DBAT5L     /* Data BAT 5 Lower Register */
+#define        DBAT5U  SPRN_DBAT5U     /* Data BAT 5 Upper Register */
+#define        DBAT6L  SPRN_DBAT6L     /* Data BAT 6 Lower Register */
+#define        DBAT6U  SPRN_DBAT6U     /* Data BAT 6 Upper Register */
+#define        DBAT7L  SPRN_DBAT7L     /* Data BAT 7 Lower Register */
+#define        DBAT7U  SPRN_DBAT7U     /* Data BAT 7 Upper Register */
 #define        DCMP    SPRN_DCMP       /* Data TLB Compare Register */
 #define        DEC     SPRN_DEC        /* Decrement Register */
 #define        DMISS   SPRN_DMISS      /* Data TLB Miss Register */
@@ -323,6 +347,14 @@
 #define        IBAT2U  SPRN_IBAT2U     /* Instruction BAT 2 Upper Register */
 #define        IBAT3L  SPRN_IBAT3L     /* Instruction BAT 3 Lower Register */
 #define        IBAT3U  SPRN_IBAT3U     /* Instruction BAT 3 Upper Register */
+#define        IBAT4L  SPRN_IBAT4L     /* Instruction BAT 4 Lower Register */
+#define        IBAT4U  SPRN_IBAT4U     /* Instruction BAT 4 Upper Register */
+#define        IBAT5L  SPRN_IBAT5L     /* Instruction BAT 5 Lower Register */
+#define        IBAT5U  SPRN_IBAT5U     /* Instruction BAT 5 Upper Register */
+#define        IBAT6L  SPRN_IBAT6L     /* Instruction BAT 6 Lower Register */
+#define        IBAT6U  SPRN_IBAT6U     /* Instruction BAT 6 Upper Register */
+#define        IBAT7L  SPRN_IBAT7L     /* Instruction BAT 7 Lower Register */
+#define        IBAT7U  SPRN_IBAT7U     /* Instruction BAT 7 Lower Register */
 #define        ICMP    SPRN_ICMP       /* Instruction TLB Compare Register */
 #define        IMISS   SPRN_IMISS      /* Instruction TLB Miss Register */
 #define        IMMR    SPRN_IMMR       /* PPC 860/821 Internal Memory Map Register */