mmr_unlock(PADCFG_MMR1_BASE, 1);
}
-#if (IS_ENABLED(CONFIG_CPU_V7R))
-static void setup_qos(void)
-{
- u32 i;
-
- for (i = 0; i < am62a_qos_count; i++)
- writel(am62a_qos_data[i].val, (uintptr_t)am62a_qos_data[i].reg);
-}
-#else
-static void setup_qos(void)
-{
-}
-#endif
-
void board_init_f(ulong dummy)
{
struct udevice *dev;
#include <elf.h>
#include <soc.h>
+#include <asm/arch/k3-qos.h>
+
#if IS_ENABLED(CONFIG_SYS_K3_SPL_ATF)
enum {
IMAGE_ID_ATF,
void __weak do_board_detect(void)
{
}
+
+#if (IS_ENABLED(CONFIG_K3_QOS))
+void setup_qos(void)
+{
+ u32 i;
+
+ for (i = 0; i < qos_count; i++)
+ writel(qos_data[i].val, (uintptr_t)qos_data[i].reg);
+}
+#endif
struct ti_sci_handle *get_ti_sci_handle(void);
void do_board_detect(void);
void ti_secure_image_check_binary(void **p_image, size_t *p_size);
+
+#if (IS_ENABLED(CONFIG_K3_QOS))
+void setup_qos(void);
+#else
+static inline void setup_qos(void)
+{
+}
+#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Keystone3 Quality of service endpoint definitions
- * Auto generated by K3 Resource Partitioning Tool
- *
- * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#define QOS_0 (0 << 0)
-#define QOS_1 (1 << 0)
-#define QOS_2 (2 << 0)
-#define QOS_3 (3 << 0)
-#define QOS_4 (4 << 0)
-#define QOS_5 (5 << 0)
-#define QOS_6 (6 << 0)
-#define QOS_7 (7 << 0)
-
-#define ORDERID_0 (0 << 4)
-#define ORDERID_1 (1 << 4)
-#define ORDERID_2 (2 << 4)
-#define ORDERID_3 (3 << 4)
-#define ORDERID_4 (4 << 4)
-#define ORDERID_5 (5 << 4)
-#define ORDERID_6 (6 << 4)
-#define ORDERID_7 (7 << 4)
-#define ORDERID_8 (8 << 4)
-#define ORDERID_9 (9 << 4)
-#define ORDERID_10 (10 << 4)
-#define ORDERID_11 (11 << 4)
-#define ORDERID_12 (12 << 4)
-#define ORDERID_13 (13 << 4)
-#define ORDERID_14 (14 << 4)
-#define ORDERID_15 (15 << 4)
-
-#define ASEL_0 (0 << 8)
-#define ASEL_1 (1 << 8)
-#define ASEL_2 (2 << 8)
-#define ASEL_3 (3 << 8)
-#define ASEL_4 (4 << 8)
-#define ASEL_5 (5 << 8)
-#define ASEL_6 (6 << 8)
-#define ASEL_7 (7 << 8)
-#define ASEL_8 (8 << 8)
-#define ASEL_9 (9 << 8)
-#define ASEL_10 (10 << 8)
-#define ASEL_11 (11 << 8)
-#define ASEL_12 (12 << 8)
-#define ASEL_13 (13 << 8)
-#define ASEL_14 (14 << 8)
-#define ASEL_15 (15 << 8)
-
-#define EPRIORITY_0 (0 << 12)
-#define EPRIORITY_1 (1 << 12)
-#define EPRIORITY_2 (2 << 12)
-#define EPRIORITY_3 (3 << 12)
-#define EPRIORITY_4 (4 << 12)
-#define EPRIORITY_5 (5 << 12)
-#define EPRIORITY_6 (6 << 12)
-#define EPRIORITY_7 (7 << 12)
-
-#define VIRTID_0 (0 << 16)
-#define VIRTID_1 (1 << 16)
-#define VIRTID_2 (2 << 16)
-#define VIRTID_3 (3 << 16)
-#define VIRTID_4 (4 << 16)
-#define VIRTID_5 (5 << 16)
-#define VIRTID_6 (6 << 16)
-#define VIRTID_7 (7 << 16)
-#define VIRTID_8 (8 << 16)
-#define VIRTID_9 (9 << 16)
-#define VIRTID_10 (10 << 16)
-#define VIRTID_11 (11 << 16)
-#define VIRTID_12 (12 << 16)
-#define VIRTID_13 (13 << 16)
-#define VIRTID_14 (14 << 16)
-#define VIRTID_15 (15 << 16)
-
-#define ATYPE_0 (0 << 28)
-#define ATYPE_1 (1 << 28)
-#define ATYPE_2 (2 << 28)
-#define ATYPE_3 (3 << 28)
-
-#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
-#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
-#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
-#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
-#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
-#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
-#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
-#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
-#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
-#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
-#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
-#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
-#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800
-#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00
-#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
-#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
-#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
-#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
-#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000
-#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400
-#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800
-#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00
-#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000
-#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
-#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800
-#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00
-#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
-#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
-#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
-#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
-#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800
-#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000
#ifdef CONFIG_SOC_K3_AM62A7
#include "am62a_hardware.h"
-#include "am62a_qos.h"
#endif
/* Assuming these addresses and definitions stay common across K3 devices */
u32 num_components;
};
-struct k3_qos_data {
- u32 reg;
- u32 val;
-};
-
-extern struct k3_qos_data am62a_qos_data[];
-extern u32 am62a_qos_count;
-
#endif /* _ASM_ARCH_HARDWARE_H_ */
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Quality of Service (QoS) Configuration Header File
+ *
+ * Copyright (C) 2024 Texas Instruments Incorporated - https://www.ti.com/
+ */
+#ifndef _K3_QOS_H_
+#define _K3_QOS_H_
+
+#include <linux/kernel.h>
+
+struct k3_qos_data {
+ u32 reg;
+ u32 val;
+};
+
+#if (IS_ENABLED(CONFIG_K3_QOS))
+extern struct k3_qos_data qos_data[];
+extern u32 qos_count;
+#endif
+
+#endif /* _K3_QOS_H_ */
config K3_LOAD_SYSFW
bool
+config K3_QOS
+ bool "Enable Quality of Service (QoS) Settings for TI K3 SoCs"
+ default y if SOC_K3_AM62A7
+ help
+ This option enables the R5 SPL to apply QoS settings for various
+ HW controllers inside the TI K3 SoCs. The files for QoS settings are
+ generated from Sysconfig and k3-resource-partitioning tools.
+
config K3_SYSFW_IMAGE_NAME
string "File name of SYSFW firmware and configuration blob"
depends on K3_LOAD_SYSFW
obj-y += clk-data.o
obj-y += dev-data.o
-obj-y += am62a_qos_data.o
+obj-y += am62a_qos_uboot.o
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Keystone3 Quality of service endpoint definitions
+ * Auto generated by K3 Resource Partitioning Tool
+ *
+ * Copyright (C) 2023 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#define QOS_0 (0 << 0)
+#define QOS_1 (1 << 0)
+#define QOS_2 (2 << 0)
+#define QOS_3 (3 << 0)
+#define QOS_4 (4 << 0)
+#define QOS_5 (5 << 0)
+#define QOS_6 (6 << 0)
+#define QOS_7 (7 << 0)
+
+#define ORDERID_0 (0 << 4)
+#define ORDERID_1 (1 << 4)
+#define ORDERID_2 (2 << 4)
+#define ORDERID_3 (3 << 4)
+#define ORDERID_4 (4 << 4)
+#define ORDERID_5 (5 << 4)
+#define ORDERID_6 (6 << 4)
+#define ORDERID_7 (7 << 4)
+#define ORDERID_8 (8 << 4)
+#define ORDERID_9 (9 << 4)
+#define ORDERID_10 (10 << 4)
+#define ORDERID_11 (11 << 4)
+#define ORDERID_12 (12 << 4)
+#define ORDERID_13 (13 << 4)
+#define ORDERID_14 (14 << 4)
+#define ORDERID_15 (15 << 4)
+
+#define ASEL_0 (0 << 8)
+#define ASEL_1 (1 << 8)
+#define ASEL_2 (2 << 8)
+#define ASEL_3 (3 << 8)
+#define ASEL_4 (4 << 8)
+#define ASEL_5 (5 << 8)
+#define ASEL_6 (6 << 8)
+#define ASEL_7 (7 << 8)
+#define ASEL_8 (8 << 8)
+#define ASEL_9 (9 << 8)
+#define ASEL_10 (10 << 8)
+#define ASEL_11 (11 << 8)
+#define ASEL_12 (12 << 8)
+#define ASEL_13 (13 << 8)
+#define ASEL_14 (14 << 8)
+#define ASEL_15 (15 << 8)
+
+#define EPRIORITY_0 (0 << 12)
+#define EPRIORITY_1 (1 << 12)
+#define EPRIORITY_2 (2 << 12)
+#define EPRIORITY_3 (3 << 12)
+#define EPRIORITY_4 (4 << 12)
+#define EPRIORITY_5 (5 << 12)
+#define EPRIORITY_6 (6 << 12)
+#define EPRIORITY_7 (7 << 12)
+
+#define VIRTID_0 (0 << 16)
+#define VIRTID_1 (1 << 16)
+#define VIRTID_2 (2 << 16)
+#define VIRTID_3 (3 << 16)
+#define VIRTID_4 (4 << 16)
+#define VIRTID_5 (5 << 16)
+#define VIRTID_6 (6 << 16)
+#define VIRTID_7 (7 << 16)
+#define VIRTID_8 (8 << 16)
+#define VIRTID_9 (9 << 16)
+#define VIRTID_10 (10 << 16)
+#define VIRTID_11 (11 << 16)
+#define VIRTID_12 (12 << 16)
+#define VIRTID_13 (13 << 16)
+#define VIRTID_14 (14 << 16)
+#define VIRTID_15 (15 << 16)
+
+#define ATYPE_0 (0 << 28)
+#define ATYPE_1 (1 << 28)
+#define ATYPE_2 (2 << 28)
+#define ATYPE_3 (3 << 28)
+
+#define PULSAR_UL_WKUP_0_CPU0_RMST 0x45D14000
+#define PULSAR_UL_WKUP_0_CPU0_WMST 0x45D14400
+#define PULSAR_UL_WKUP_0_CPU0_PMST 0x45D14800
+#define PULSAR_ULS_MCU_0_CPU0_RMST 0x45D18000
+#define PULSAR_ULS_MCU_0_CPU0_WMST 0x45D18400
+#define PULSAR_ULS_MCU_0_CPU0_PMST 0x45D18800
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_R 0x45D20400
+#define SAM62A_A53_512KB_WRAP_MAIN_0_A53_QUAD_WRAP_CBA_AXI_W 0x45D20800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMW 0x45D21800
+#define DEBUGSS_K3_WRAP_CV0_MAIN_0_VBUSMR 0x45D21C00
+#define GIC500SS_1_4_MAIN_0_MEM_WR_VBUSM 0x45D22000
+#define GIC500SS_1_4_MAIN_0_MEM_RD_VBUSM 0x45D22400
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_RD 0x45D22800
+#define EMMCSD8SS_MAIN_0_EMMCSDSS_WR 0x45D22C00
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_RD 0x45D23000
+#define EMMCSD4SS_MAIN_0_EMMCSDSS_WR 0x45D23400
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_WR 0x45D23800
+#define EMMCSD4SS_MAIN_1_EMMCSDSS_RD 0x45D23C00
+#define USB2SS_16FFC_MAIN_0_MSTW0 0x45D24000
+#define USB2SS_16FFC_MAIN_0_MSTR0 0x45D24400
+#define USB2SS_16FFC_MAIN_1_MSTR0 0x45D24800
+#define USB2SS_16FFC_MAIN_1_MSTW0 0x45D24C00
+#define K3_DSS_UL_MAIN_0_VBUSM_DMA 0x45D25000
+#define SA3SS_AM62A_MAIN_0_CTXCACH_EXT_DMA 0x45D25400
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_W 0x45D25800
+#define K3_JPGENC_E5010_MAIN_0_M_VBUSM_R 0x45D25C00
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_R_ASYNC 0x45D26800
+#define K3_VPU_WAVE521CL_MAIN_0_PRI_M_VBUSM_W_ASYNC 0x45D26C00
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_R_ASYNC 0x45D27000
+#define K3_VPU_WAVE521CL_MAIN_0_SEC_M_VBUSM_W_ASYNC 0x45D27400
+#define SAM62A_C7XV_WRAP_MAIN_0_C7XV_SOC 0x45D27800
+#define SAM62A_VPAC_WRAP_MAIN_0_LDC0_M_MST 0x45D28000
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * am62a Quality of Service (QoS) Configuration Data
- * Auto generated from K3 Resource Partitioning tool
- *
- * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
- */
-#include <asm/arch/hardware.h>
-#include "common.h"
-
-struct k3_qos_data am62a_qos_data[] = {
- /* modules_qosConfig0 - 1 endpoints, 4 channels */
- {
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
- .val = ORDERID_8,
- },
- {
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
- .val = ORDERID_8,
- },
- {
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
- .val = ORDERID_8,
- },
- {
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
- .val = ORDERID_8,
- },
-
- /* Following registers set 1:1 mapping for orderID MAP1/MAP2
- * remap registers. orderID x is remapped to orderID x again
- * This is to ensure orderID from MAP register is unchanged
- */
-
- /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
- {
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
- .val = 0x76543210,
- },
- {
- .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
- .val = 0xfedcba98,
- },
-};
-
-uint32_t am62a_qos_count = sizeof(am62a_qos_data) / sizeof(am62a_qos_data[0]);
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * am62a Quality of Service (QoS) Configuration Data
+ * Auto generated from K3 Resource Partitioning tool
+ *
+ * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/
+ */
+
+#include <asm/arch/k3-qos.h>
+#include "am62a_qos.h"
+
+struct k3_qos_data qos_data[] = {
+ /* modules_qosConfig0 - 1 endpoints, 4 channels */
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 0,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 1,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 2,
+ .val = ORDERID_8,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0x100 + 0x4 * 3,
+ .val = ORDERID_8,
+ },
+
+ /* Following registers set 1:1 mapping for orderID MAP1/MAP2
+ * remap registers. orderID x is remapped to orderID x again
+ * This is to ensure orderID from MAP register is unchanged
+ */
+
+ /* K3_DSS_UL_MAIN_0_VBUSM_DMA - 1 groups */
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 0,
+ .val = 0x76543210,
+ },
+ {
+ .reg = K3_DSS_UL_MAIN_0_VBUSM_DMA + 4,
+ .val = 0xfedcba98,
+ },
+};
+
+u32 qos_count = ARRAY_SIZE(qos_data);
projects / platform / kernel / u-boot.git / commitdiff