int nv46_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int nv4c_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int g84_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
-int g94_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
+int g92_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int gf100_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int gf106_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
int gk104_pci_new(struct nvkm_device *, int, struct nvkm_pci **);
.mc = g84_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.mc = g84_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.mc = g98_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.mc = g84_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.mc = gt215_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
.mc = gt215_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
.mc = gt215_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
.mc = g98_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.mc = g98_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.therm = g84_therm_new,
.timer = nv41_timer_new,
.volt = nv40_volt_new,
.mc = gt215_mc_new,
.mmu = nv50_mmu_new,
.mxm = nv50_mxm_new,
- .pci = g94_pci_new,
+ .pci = g92_pci_new,
.pmu = gt215_pmu_new,
.therm = gt215_therm_new,
.timer = nv41_timer_new,
nvkm-y += nvkm/subdev/pci/nv46.o
nvkm-y += nvkm/subdev/pci/nv4c.o
nvkm-y += nvkm/subdev/pci/g84.o
-nvkm-y += nvkm/subdev/pci/g94.o
+nvkm-y += nvkm/subdev/pci/g92.o
nvkm-y += nvkm/subdev/pci/gf100.o
nvkm-y += nvkm/subdev/pci/gf106.o
nvkm-y += nvkm/subdev/pci/gk104.o
#include "priv.h"
int
-g94_pcie_version_supported(struct nvkm_pci *pci)
+g92_pcie_version_supported(struct nvkm_pci *pci)
{
if ((nvkm_pci_rd32(pci, 0x460) & 0x200) == 0x200)
return 2;
}
static const struct nvkm_pci_func
-g94_pci_func = {
+g92_pci_func = {
.init = g84_pci_init,
.rd32 = nv40_pci_rd32,
.wr08 = nv40_pci_wr08,
.pcie.set_version = g84_pcie_set_version,
.pcie.version = g84_pcie_version,
- .pcie.version_supported = g94_pcie_version_supported,
+ .pcie.version_supported = g92_pcie_version_supported,
};
int
-g94_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
+g92_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
{
- return nvkm_pci_new_(&g94_pci_func, device, index, ppci);
+ return nvkm_pci_new_(&g92_pci_func, device, index, ppci);
}
.pcie.set_version = gf100_pcie_set_version,
.pcie.version = gf100_pcie_version,
- .pcie.version_supported = g94_pcie_version_supported,
+ .pcie.version_supported = g92_pcie_version_supported,
};
int
.pcie.set_version = gf100_pcie_set_version,
.pcie.version = gf100_pcie_version,
- .pcie.version_supported = g94_pcie_version_supported,
+ .pcie.version_supported = g92_pcie_version_supported,
};
int
int g84_pcie_init(struct nvkm_pci *);
int g84_pcie_set_link(struct nvkm_pci *, enum nvkm_pcie_speed, u8);
-int g94_pcie_version_supported(struct nvkm_pci *);
+int g92_pcie_version_supported(struct nvkm_pci *);
void gf100_pcie_set_version(struct nvkm_pci *, u8);
int gf100_pcie_version(struct nvkm_pci *);