- [ls][dw][lr] report broken (aligned) BadVAddr
- Missing per-CPU instruction decoding, currently all implemented
instructions are regarded as valid
-- pcnet32 does not work for little endian emulation on big endian host
- (probably not mips specific, but observable for mips-malta)
-- CP1 enable/disable is checked at translation time, not at execution
- time, so it will have delayed effect.
MIPS64
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- We fake firmware support instead of doing the real thing
- Real firmware falls over when trying to init RAM, presumably due
- to lacking I2C emulation.
+ to lacking system controller emulation.