i2c_slave slave;
i2c_bus *bus;
qemu_irq irq;
+ target_phys_addr_t offset;
uint16_t control;
uint16_t status;
{
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
- addr &= 0xff;
+ addr -= s->offset;
switch (addr) {
case ICR:
return s->control;
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
int ack;
- addr &= 0xff;
+ addr -= s->offset;
switch (addr) {
case ICR:
s->control = value & 0xfff7;
}
struct pxa2xx_i2c_s *pxa2xx_i2c_init(target_phys_addr_t base,
- qemu_irq irq, uint32_t page_size)
+ qemu_irq irq, uint32_t region_size)
{
int iomemtype;
/* FIXME: Should the slave device really be on a separate bus? */
s->slave.recv = pxa2xx_i2c_rx;
s->slave.send = pxa2xx_i2c_tx;
s->bus = i2c_init_bus();
+ s->offset = base & region_size;
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
pxa2xx_i2c_writefn, s);
- cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype);
+ cpu_register_physical_memory(base & ~region_size,
+ region_size + 1, iomemtype);
register_savevm("pxa2xx_i2c", base, 1,
pxa2xx_i2c_save, pxa2xx_i2c_load, s);