}
if (sctx->compute_scratch_buffer != shader->scratch_bo && scratch_needed) {
- if (sctx->gfx_level < GFX11) {
+ if (sctx->gfx_level < GFX11 &&
+ (sctx->family < CHIP_GFX940 || sctx->screen->info.has_graphics)) {
uint64_t scratch_va = sctx->compute_scratch_buffer->gpu_address;
if (!si_shader_binary_upload(sctx->screen, shader, scratch_va))
S_00B8A0_INST_PREF_SIZE(si_get_shader_prefetch_size(shader)));
}
- if (sctx->gfx_level >= GFX11 && shader->scratch_bo) {
+ if ((sctx->gfx_level >= GFX11 ||
+ (sctx->family >= CHIP_GFX940 && !sctx->screen->info.has_graphics)) &&
+ shader->scratch_bo) {
radeon_set_sh_reg_seq(R_00B840_COMPUTE_DISPATCH_SCRATCH_BASE_LO, 4);
radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 8);
radeon_emit(sctx->compute_scratch_buffer->gpu_address >> 40);
/* Add the scratch offset to input SGPRs. */
if (sel->screen->info.gfx_level < GFX11 &&
+ (sel->screen->info.family < CHIP_GFX940 || sel->screen->info.has_graphics) &&
shader->config.scratch_bytes_per_wave && !si_is_merged_shader(shader))
shader->info.num_input_sgprs += 1; /* scratch byte offset */