arm64: dts: renesas: rzg2: Add reset control properties for display

Add reset control properties to the device nodes for the Display Units
on all supported RZ/G2 SoCs.  Note that on these SoCs, there is only a
single reset for each pair of DU channels.

Join the clocks lines while at it, to increase uniformity.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Link: https://lore.kernel.org/r/20200218133019.22299-5-geert+renesas@glider.be

diff --git a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
index 507e78e..7902343 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774a1.dtsi
@@ -2634,10 +2634,11 @@
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 269 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 724>,
-                                <&cpg CPG_MOD 723>,
+                       clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
                                 <&cpg CPG_MOD 722>;
                        clock-names = "du.0", "du.1", "du.2";
+                       resets = <&cpg 724>, <&cpg 722>;
+                       reset-names = "du.0", "du.2";
                        status = "disabled";
 
                        renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd2 0>;

diff --git a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
index 93dd10b..3137f73 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774b1.dtsi
@@ -2480,10 +2480,11 @@
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 270 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 724>,
-                                <&cpg CPG_MOD 723>,
+                       clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>,
                                 <&cpg CPG_MOD 721>;
                        clock-names = "du.0", "du.1", "du.3";
+                       resets = <&cpg 724>, <&cpg 722>;
+                       reset-names = "du.0", "du.3";
                        status = "disabled";
 
                        renesas,vsps = <&vspd0 0>, <&vspd1 0>, <&vspd0 1>;

diff --git a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
index d4eee8f..22785cb 100644 (file)
--- a/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a774c0.dtsi
@@ -1810,9 +1810,10 @@
                        reg = <0 0xfeb00000 0 0x40000>;
                        interrupts = <GIC_SPI 256 IRQ_TYPE_LEVEL_HIGH>,
                                     <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&cpg CPG_MOD 724>,
-                                <&cpg CPG_MOD 723>;
+                       clocks = <&cpg CPG_MOD 724>, <&cpg CPG_MOD 723>;
                        clock-names = "du.0", "du.1";
+                       resets = <&cpg 724>;
+                       reset-names = "du.0";
                        renesas,vsps = <&vspd0 0>, <&vspd1 0>;
 
                        status = "disabled";