mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte

Cypress chips support SPINOR_OP_EN4B(B7h) to enable 4-byte addressing mode.

Cypress chips support B8h to disable 4-byte addressing mode instead of
SPINOR_OP_EX4B(E9h).

This patch defines new opcode and updates set_4byte() to support
enable/disable 4-byte addressing mode for Cypress chips.

Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>

diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c
index 7f1ed1b..94dfa97 100644 (file)
--- a/drivers/mtd/spi/spi-nor-core.c
+++ b/drivers/mtd/spi/spi-nor-core.c
@@ -662,6 +662,9 @@ static int set_4byte(struct spi_nor *nor, const struct flash_info *info,
                }
 
                return status;
+       case SNOR_MFR_CYPRESS:
+               cmd = enable ? SPINOR_OP_EN4B : SPINOR_OP_EX4B_CYPRESS;
+               return nor->write_reg(nor, cmd, NULL, 0);
        default:
                /* Spansion style */
                nor->cmd_buf[0] = enable << 7;

diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h
index b9d6645..6df82bd 100644 (file)
--- a/include/linux/mtd/spi-nor.h
+++ b/include/linux/mtd/spi-nor.h
@@ -123,6 +123,7 @@
 #define SPINOR_OP_BRWR         0x17    /* Bank register write */
 #define SPINOR_OP_BRRD         0x16    /* Bank register read */
 #define SPINOR_OP_CLSR         0x30    /* Clear status register 1 */
+#define SPINOR_OP_EX4B_CYPRESS 0xB8    /* Exit 4-byte mode */
 #define SPINOR_OP_RDAR         0x65    /* Read any register */
 #define SPINOR_OP_WRAR         0x71    /* Write any register */
 #define SPINOR_REG_ADDR_STR1V  0x00800000