drm/i915/skl: Fix the CTRL typo in the DPLL_CRTL1 defines

Signed-off-by: Damien Lespiau <damien.lespiau@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 136d42a..51baca1 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -295,7 +295,7 @@ struct intel_dpll_hw_state {
        /* skl */
        /*
         * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
-        * lower part of crtl1 and they get shifted into position when writing
+        * lower part of ctrl1 and they get shifted into position when writing
         * the register.  This allows us to easily compare the state to share
         * the DPLL.
         */

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1d4871b..8924f4b 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7141,16 +7141,16 @@ enum skl_disp_power_wells {
 #define DPLL_CTRL1             0x6C058
 #define  DPLL_CTRL1_HDMI_MODE(id)              (1<<((id)*6+5))
 #define  DPLL_CTRL1_SSC(id)                    (1<<((id)*6+4))
-#define  DPLL_CRTL1_LINK_RATE_MASK(id)         (7<<((id)*6+1))
-#define  DPLL_CRTL1_LINK_RATE_SHIFT(id)                ((id)*6+1)
-#define  DPLL_CRTL1_LINK_RATE(linkrate, id)    ((linkrate)<<((id)*6+1))
+#define  DPLL_CTRL1_LINK_RATE_MASK(id)         (7<<((id)*6+1))
+#define  DPLL_CTRL1_LINK_RATE_SHIFT(id)                ((id)*6+1)
+#define  DPLL_CTRL1_LINK_RATE(linkrate, id)    ((linkrate)<<((id)*6+1))
 #define  DPLL_CTRL1_OVERRIDE(id)               (1<<((id)*6))
-#define  DPLL_CRTL1_LINK_RATE_2700             0
-#define  DPLL_CRTL1_LINK_RATE_1350             1
-#define  DPLL_CRTL1_LINK_RATE_810              2
-#define  DPLL_CRTL1_LINK_RATE_1620             3
-#define  DPLL_CRTL1_LINK_RATE_1080             4
-#define  DPLL_CRTL1_LINK_RATE_2160             5
+#define  DPLL_CTRL1_LINK_RATE_2700             0
+#define  DPLL_CTRL1_LINK_RATE_1350             1
+#define  DPLL_CTRL1_LINK_RATE_810              2
+#define  DPLL_CTRL1_LINK_RATE_1620             3
+#define  DPLL_CTRL1_LINK_RATE_1080             4
+#define  DPLL_CTRL1_LINK_RATE_2160             5
 
 /* DPLL control2 */
 #define DPLL_CTRL2                             0x6C05C

diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 9c1e74a..d5bee8b 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -870,26 +870,26 @@ static void skl_ddi_clock_get(struct intel_encoder *encoder,
        if (dpll_ctl1 & DPLL_CTRL1_HDMI_MODE(dpll)) {
                link_clock = skl_calc_wrpll_link(dev_priv, dpll);
        } else {
-               link_clock = dpll_ctl1 & DPLL_CRTL1_LINK_RATE_MASK(dpll);
-               link_clock >>= DPLL_CRTL1_LINK_RATE_SHIFT(dpll);
+               link_clock = dpll_ctl1 & DPLL_CTRL1_LINK_RATE_MASK(dpll);
+               link_clock >>= DPLL_CTRL1_LINK_RATE_SHIFT(dpll);
 
                switch (link_clock) {
-               case DPLL_CRTL1_LINK_RATE_810:
+               case DPLL_CTRL1_LINK_RATE_810:
                        link_clock = 81000;
                        break;
-               case DPLL_CRTL1_LINK_RATE_1080:
+               case DPLL_CTRL1_LINK_RATE_1080:
                        link_clock = 108000;
                        break;
-               case DPLL_CRTL1_LINK_RATE_1350:
+               case DPLL_CTRL1_LINK_RATE_1350:
                        link_clock = 135000;
                        break;
-               case DPLL_CRTL1_LINK_RATE_1620:
+               case DPLL_CTRL1_LINK_RATE_1620:
                        link_clock = 162000;
                        break;
-               case DPLL_CRTL1_LINK_RATE_2160:
+               case DPLL_CTRL1_LINK_RATE_2160:
                        link_clock = 216000;
                        break;
-               case DPLL_CRTL1_LINK_RATE_2700:
+               case DPLL_CTRL1_LINK_RATE_2700:
                        link_clock = 270000;
                        break;
                default:
@@ -1294,13 +1294,13 @@ skl_ddi_pll_select(struct intel_crtc *intel_crtc,
 
                switch (intel_dp->link_bw) {
                case DP_LINK_BW_1_62:
-                       ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810, 0);
+                       ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
                        break;
                case DP_LINK_BW_2_7:
-                       ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350, 0);
+                       ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
                        break;
                case DP_LINK_BW_5_4:
-                       ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700, 0);
+                       ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
                        break;
                }
 
@@ -1854,7 +1854,7 @@ static void intel_ddi_pre_enable(struct intel_encoder *intel_encoder)
 
                        val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) |
                                 DPLL_CTRL1_SSC(dpll) |
-                                DPLL_CRTL1_LINK_RATE_MASK(dpll));
+                                DPLL_CTRL1_LINK_RATE_MASK(dpll));
                        val |= crtc->config->dpll_hw_state.ctrl1 << (dpll * 6);
 
                        I915_WRITE(DPLL_CTRL1, val);
@@ -2100,7 +2100,7 @@ static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
        val = I915_READ(DPLL_CTRL1);
 
        val &= ~(DPLL_CTRL1_HDMI_MODE(dpll) | DPLL_CTRL1_SSC(dpll) |
-                DPLL_CRTL1_LINK_RATE_MASK(dpll));
+                DPLL_CTRL1_LINK_RATE_MASK(dpll));
        val |= pll->config.hw_state.ctrl1 << (dpll * 6);
 
        I915_WRITE(DPLL_CTRL1, val);

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index abbca0e..8e21e23 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -6467,10 +6467,10 @@ static int skylake_get_display_clock_speed(struct drm_device *dev)
                return 540000;
 
        linkrate = (I915_READ(DPLL_CTRL1) &
-                   DPLL_CRTL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
+                   DPLL_CTRL1_LINK_RATE_MASK(SKL_DPLL0)) >> 1;
 
-       if (linkrate == DPLL_CRTL1_LINK_RATE_2160 ||
-           linkrate == DPLL_CRTL1_LINK_RATE_1080) {
+       if (linkrate == DPLL_CTRL1_LINK_RATE_2160 ||
+           linkrate == DPLL_CTRL1_LINK_RATE_1080) {
                /* vco 8640 */
                switch (cdctl & CDCLK_FREQ_SEL_MASK) {
                case CDCLK_FREQ_450_432:

diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 7c3dbd4..5e978d6 100644 (file)
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -1098,30 +1098,30 @@ skl_edp_set_pll_config(struct intel_crtc_state *pipe_config, int link_clock)
        ctrl1 = DPLL_CTRL1_OVERRIDE(SKL_DPLL0);
        switch (link_clock / 2) {
        case 81000:
-               ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_810,
+               ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810,
                                              SKL_DPLL0);
                break;
        case 135000:
-               ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1350,
+               ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350,
                                              SKL_DPLL0);
                break;
        case 270000:
-               ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2700,
+               ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700,
                                              SKL_DPLL0);
                break;
        case 162000:
-               ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1620,
+               ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620,
                                              SKL_DPLL0);
                break;
        /* TBD: For DP link rates 2.16 GHz and 4.32 GHz, VCO is 8640 which
        results in CDCLK change. Need to handle the change of CDCLK by
        disabling pipes and re-enabling them */
        case 108000:
-               ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_1080,
+               ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080,
                                              SKL_DPLL0);
                break;
        case 216000:
-               ctrl1 |= DPLL_CRTL1_LINK_RATE(DPLL_CRTL1_LINK_RATE_2160,
+               ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160,
                                              SKL_DPLL0);
                break;