*/
int board_init(void)
{
+#if defined(CONFIG_CMD_ONENAND)
+ const u32 gpmc_regs_onenandrx51[GPMC_MAX_REG] = {
+ ONENAND_GPMC_CONFIG1_RX51,
+ ONENAND_GPMC_CONFIG2_RX51,
+ ONENAND_GPMC_CONFIG3_RX51,
+ ONENAND_GPMC_CONFIG4_RX51,
+ ONENAND_GPMC_CONFIG5_RX51,
+ ONENAND_GPMC_CONFIG6_RX51,
+ 0
+ };
+#endif
/* in SRAM or SDRAM, finish GPMC */
gpmc_init();
+#if defined(CONFIG_CMD_ONENAND)
+ enable_gpmc_cs_config(gpmc_regs_onenandrx51, &gpmc_cfg->cs[0],
+ CONFIG_SYS_ONENAND_BASE, GPMC_SIZE_256M);
+#endif
/* Enable the clks & power */
per_clocks_enable();
/* boot param addr */
MUX_VAL(CP(UART2_RTS), (IDIS | PTD | DIS | M0)) /*UART2_RTS*/\
MUX_VAL(CP(UART2_TX), (IDIS | PTD | DIS | M0)) /*UART2_TX*/
+#define ONENAND_GPMC_CONFIG1_RX51 0xfb001202
+#define ONENAND_GPMC_CONFIG2_RX51 0x00111100
+#define ONENAND_GPMC_CONFIG3_RX51 0x00020200
+#define ONENAND_GPMC_CONFIG4_RX51 0x11001102
+#define ONENAND_GPMC_CONFIG5_RX51 0x03101616
+#define ONENAND_GPMC_CONFIG6_RX51 0x90060000
+
#endif