[why]
Link rate in kHz is what is eventually required to calculate the link
bandwidth, which makes kHz a more generic unit. This should also make
forward-compatibility with new DP standards easier.
[how]
- Replace 'link rate DPCD code' with 'link rate in kHz' when used with
drm_dp_mst_topology_mgr_init()
- Add/remove related DPCD code conversion from/to kHz where applicable
Signed-off-by: Nikola Cornij <nikola.cornij@amd.com>
Acked-by: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20210512210011.8425-2-nikola.cornij@amd.com
&aconnector->dm_dp_aux.aux,
16,
4,
- (u8)max_link_enc_cap.lane_count,
- (u8)max_link_enc_cap.link_rate,
+ max_link_enc_cap.lane_count,
+ drm_dp_bw_code_to_link_rate(max_link_enc_cap.link_rate),
aconnector->connector_id);
drm_connector_attach_dp_subconnector_property(&aconnector->base);
}
lane_count = min_t(int, mgr->dpcd[2] & DP_MAX_LANE_COUNT_MASK, mgr->max_lane_count);
- link_rate = min_t(int, mgr->dpcd[1], mgr->max_link_rate);
+ link_rate = min_t(int, drm_dp_bw_code_to_link_rate(mgr->dpcd[1]), mgr->max_link_rate);
mgr->pbn_div = drm_dp_get_vc_payload_bw(mgr,
- drm_dp_bw_code_to_link_rate(link_rate),
+ link_rate,
lane_count);
if (mgr->pbn_div == 0) {
ret = -EINVAL;
* @max_dpcd_transaction_bytes: hw specific DPCD transaction limit
* @max_payloads: maximum number of payloads this GPU can source
* @max_lane_count: maximum number of lanes this GPU supports
- * @max_link_rate: maximum link rate this GPU supports, units as in DPCD
+ * @max_link_rate: maximum link rate per lane this GPU supports in kHz
* @conn_base_id: the connector object ID the MST device is connected to.
*
* Return 0 for success, or negative error code on failure
int drm_dp_mst_topology_mgr_init(struct drm_dp_mst_topology_mgr *mgr,
struct drm_device *dev, struct drm_dp_aux *aux,
int max_dpcd_transaction_bytes, int max_payloads,
- u8 max_lane_count, u8 max_link_rate,
+ int max_lane_count, int max_link_rate,
int conn_base_id)
{
struct drm_dp_mst_topology_state *mst_state;
intel_dp_create_fake_mst_encoders(dig_port);
ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm,
&intel_dp->aux, 16, 3,
- (u8)dig_port->max_lanes,
- drm_dp_link_rate_to_bw_code(max_source_rate),
+ dig_port->max_lanes,
+ max_source_rate,
conn_base_id);
if (ret)
return ret;
mstm->mgr.cbs = &nv50_mstm;
ret = drm_dp_mst_topology_mgr_init(&mstm->mgr, dev, aux, aux_max,
- (u8)max_payloads, outp->dcb->dpconf.link_nr,
- (u8)outp->dcb->dpconf.link_bw, conn_base_id);
+ max_payloads, outp->dcb->dpconf.link_nr,
+ drm_dp_bw_code_to_link_rate(outp->dcb->dpconf.link_bw),
+ conn_base_id);
if (ret)
return ret;
radeon_connector->mst_mgr.cbs = &mst_cbs;
return drm_dp_mst_topology_mgr_init(&radeon_connector->mst_mgr, dev,
&radeon_connector->ddc_bus->aux, 16, 6,
- 4, (u8)max_link_rate,
+ 4, drm_dp_bw_code_to_link_rate(max_link_rate),
radeon_connector->base.base.id);
}
/**
* @max_lane_count: maximum number of lanes the GPU can drive.
*/
- u8 max_lane_count;
+ int max_lane_count;
/**
- * @max_link_rate: maximum link rate per lane GPU can output.
+ * @max_link_rate: maximum link rate per lane GPU can output, in kHz.
*/
- u8 max_link_rate;
+ int max_link_rate;
/**
* @conn_base_id: DRM connector ID this mgr is connected to. Only used
* to build the MST connector path value.
struct drm_device *dev, struct drm_dp_aux *aux,
int max_dpcd_transaction_bytes,
int max_payloads,
- u8 max_lane_count, u8 max_link_rate,
+ int max_lane_count, int max_link_rate,
int conn_base_id);
void drm_dp_mst_topology_mgr_destroy(struct drm_dp_mst_topology_mgr *mgr);